參數(shù)資料
型號(hào)： CDB5530U
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 8/36頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR CS5530
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 24
采樣率（每秒）： 3.84k
數(shù)據(jù)接口： 串行
輸入范圍： ±2.5 V
在以下條件下的電源（標(biāo)準(zhǔn)）： 35mW @ 5V
工作溫度： -40°C ~ 85°C
已用 IC / 零件： CS5530
已供物品： 板，CD
相關(guān)產(chǎn)品： CS5530-ISZR-ND - IC ADC 24BIT 1CH W/LNA 20-SSOP
598-1283-5-ND - IC ADC 24BIT 1CH W/LNA 20SSOP
598-1198-5-ND - IC DELTA-SIGMA 24BIT 1CH 20-SSOP
其它名稱(chēng)： 598-1158
CS5530
16
DS742F3
2.2.3 Serial Port Interface
The CS5530’s serial interface consists of four con-
trol lines: CS, SDI, SDO, SCLK. Figure 7 details
the command and data word timing.
CS, Chip Select, is the control line which enables
access to the serial port. If the CS pin is tied low,
the port can function as a three wire interface.
SDI, Serial Data In, is the data signal used to trans-
fer data to the converters.
SDO, Serial Data Out, is the data signal used to
transfer output data from the converters. The SDO
output will be held at high impedance any time CS
is at logic 1.
SCLK, Serial Clock, is the serial bit-clock which
controls the shifting of data to or from the ADC’s
serial port. The CS pin must be held low (logic 0)
before SCLK transitions can be recognized by the
port logic. To accommodate optoisolators SCLK is
designed with a Schmitt-trigger input to allow an
optoisolator with slower rise and fall times to di-
rectly drive the pin. Additionally, SDO is capable
of sinking or sourcing up to 5 mA to directly drive
an optoisolator LED. SDO will have less than a 400
mV loss in the drive voltage when sinking or sourc-
ing 5 mA.
Command Time
8SCLKs
Data Time 32 SCLKs
Write Cycle
CS
SCLK
SDI
MSB
Command Time
8SCLKs
CS
SCLK
SDI
Read Cycle
SDO
MSB
LSB
Command Time
8SCLKs
8 SCLKs Clear SDO Flag
SDO
SCLK
SDI
MSB
LSB
Clock Cycles
t*
d
CS
Data Time 32 SCLKs
LSB
Data Conversion Cycle
/OWR
MCLK
* td is the time it takes the ADC to perform a conversion. See the Single
Conversion and Continuous Conversion sections of the data sheet for more
details about conversion timing.
Figure 7. Command and Data Word Timing
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