參數(shù)資料
型號： CDB5530U
廠商： Cirrus Logic Inc
文件頁數(shù)： 14/36頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR CS5530
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 24
采樣率（每秒）： 3.84k
數(shù)據(jù)接口： 串行
輸入范圍： ±2.5 V
在以下條件下的電源（標(biāo)準(zhǔn)）： 35mW @ 5V
工作溫度： -40°C ~ 85°C
已用 IC / 零件： CS5530
已供物品： 板，CD
相關(guān)產(chǎn)品： CS5530-ISZR-ND - IC ADC 24BIT 1CH W/LNA 20-SSOP
598-1283-5-ND - IC ADC 24BIT 1CH W/LNA 20SSOP
598-1198-5-ND - IC DELTA-SIGMA 24BIT 1CH 20-SSOP
其它名稱： 598-1158
CS5530
DS742F3
21
2.4 Calibration
Calibration is used to set the zero and gain slope of
the ADC’s transfer function. The CS5530 provides
system calibration.
Note:
After the ADC is reset, it is functional and can
perform measurements without being
calibrated (remember that the VRS bit in the
configuration register must be properly
configured). If the converter is operated
without calibraton, the converter will utilize
the initialized values of the on-chip registers
(Offset = 0.0; Gain = 1.0) to calculate output
words. Any initial offset and gain errors in the
internal circuitry of the chip will remain.
2.4.1 Calibration Registers
The CS5530 converter has an offset register that is
used to set the zero point of the converter’s transfer
function. As shown in Offset Register section, one
LSB in the offset register is 1.835007966 X 2-24
proportion of the input span (bipolar span is 2 times
the unipolar span, gain register = 1.000...000 deci-
mal). The MSB in the offset register determines if
the offset to be trimmed is positive or negative (0
positive, 1 negative). Note that the magnitude of
the offset that is trimmed from the input is mapped
through the gain register. The converter can typi-
cally trim ±100 percent of the input span. As shown
in the Gain Register section, the gain register spans
from 0 to (64 - 2-24). The decimal equivalent mean-
ing of the gain register is
where the binary numbers have a value of either
zero or one (bD29 is the binary value of bit D29).
While gain register settings of up to 64 - 2-24 are
available, the gain register should never be set to
values above 40.
2.4.2 Gain Register
The gain register span is from 0 to (64-2-24). After Reset D24 is 1, all other bits are ‘0’.
2.4.3 Offset Register
One LSB represents 1.835007966 X 2-24 proportion of the input span (bipolar span is 2 times unipolar span).
Offset and data word bits align by MSB. After reset, all bits are ‘0’.
The offset register is stored as a 32-bit, two’s complement number, where the last 8 bits are all 0.
Db
D29
2
5
b
D28
2
4
b
D27
2
3
… b
D0
2
24
–
)
+++
+
b
Di
2
24
–
i
+
()
i
0
=
29
==
Decimal Point
MSB
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
NU
25
24
23
22
21
20
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
000
0000
10000
0000
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
LSB
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
2-18
2-19
2-20
2-21
222
2-23
2-24
000
0000
00000
0000
MSB
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
Sign
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
000
0000
00000
0000
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
LSB
2-17
2-18
2-19
2-20
2-21
2-22
2-23
2-24
NU
000
0000
00000
0000
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