參數(shù)資料
型號(hào)： CDB5530U
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 3/36頁(yè)
文件大小： 0K
描述： BOARD EVAL FOR CS5530
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 24
采樣率（每秒）： 3.84k
數(shù)據(jù)接口： 串行
輸入范圍： ±2.5 V
在以下條件下的電源（標(biāo)準(zhǔn)）： 35mW @ 5V
工作溫度： -40°C ~ 85°C
已用 IC / 零件： CS5530
已供物品： 板，CD
相關(guān)產(chǎn)品： CS5530-ISZR-ND - IC ADC 24BIT 1CH W/LNA 20-SSOP
598-1283-5-ND - IC ADC 24BIT 1CH W/LNA 20SSOP
598-1198-5-ND - IC DELTA-SIGMA 24BIT 1CH 20-SSOP
其它名稱： 598-1158
CS5530
DS742F3
11
2. GENERAL DESCRIPTION
The CS5530 is a
ΔΣ Analog-to-Digital Converter
(ADC) which uses charge-balance techniques to
achieve 24-bit performance. The ADC is optimized
for measuring low-level unipolar or bipolar signals
in weigh scale, process control, scientific, and med-
ical applications.
To accommodate these applications, the ADC in-
cludes a very-low-noise, chopper-stabilized instru-
mentation amplifier (12 nV/
√Hz @ 0.1 Hz) with a
gain of 64X. This ADC also includes a fourth-order
ΔΣ modulator followed by a digital filter which pro-
vides twenty selectable output word rates of 6.25,
7.5, 12.5, 15, 25, 30, 50, 60, 100, 120, 200, 240, 400,
480, 800, 960, 1600, 1920, 3200, and 3840 samples
per second (MCLK = 4.9152 MHz).
To ease communication between the ADCs and a
micro-controller, the converters include a simple
three-wire serial interface which is SPI and Mi-
crowire compatible with a Schmitt-trigger input on
the serial clock (SCLK).
2.1 Analog Input
Figure 3 illustrates a block diagram of the CS5530.
The front end includes a chopper-stabilized instru-
mentation amplifier with a gain of 64X.
The amplifier is chopper-stabilized and operates with
a chop clock frequency of MCLK/128. The CVF
(sampling) current into the instrumentation amplifier
is typically 1200 pA over
-40°C to +85°C
(MCLK=4.9152 MHz). The common-mode plus sig-
nal range of the instrumentation amplifier is (VA-) +
1.6 V to (VA+) - 1.6 V.
Figure 4 illustrates the input model for the 64X am-
plifier.
Note:
The C = 3.9 pF capacitor is for input current
modeling only. For physical input capacitance
see ‘Input Capacitance’ specification under
Analog Characteristics.
VREF+
Sinc
Digital
Filter
64x
AIN+
AIN-
X1
VREF-
X1
Differential
4
Order
ΔΣ
Modulator
th
5
Programmable
Sinc
Digital Filter
3
Serial
Port
1000
Ω
1000
Ω
22 nF
C1 PIN
C2 PIN
Figure 3. Front End Configuration
AIN
C = 3.9 pF
f =
V
≤ 8 mV
i = fV
C
os
n
MCLK
128
Figure 4. Input Model for AIN+ and AIN- Pins
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