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參數(shù)資料
| 型號(hào)： | CDB5530U |
| 廠商： | Cirrus Logic Inc |
| 文件頁(yè)數(shù)： | 25/36頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR CS5530 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 3.84k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | ±2.5 V |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 35mW @ 5V |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | CS5530 |
| 已供物品： | 板，CD |
| 相關(guān)產(chǎn)品： | CS5530-ISZR-ND - IC ADC 24BIT 1CH W/LNA 20-SSOP 598-1283-5-ND - IC ADC 24BIT 1CH W/LNA 20SSOP 598-1198-5-ND - IC DELTA-SIGMA 24BIT 1CH 20-SSOP |
| 其它名稱： | 598-1158 |
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CS5530
DS742F3
31
2.11 Getting Started
This A/D converter has several features. From a
software programmer’s prospective, what should
be done first? To begin, a 4.9152 MHz or 4.096
MHz crystal takes approximately 20 ms to start. To
accommodate for this, it is recommended that a
software delay of approximately 20 ms be inserted
before the start of the processor’s ADC initializa-
tion code. Next, since the CS5530 does not provide
a power-on-reset function, the user must first ini-
tialize the ADC to a known state. This is accom-
plished by resetting the ADC’s serial port with the
Serial Port Initialization sequence. This sequence
resets the serial port to the command mode and is
accomplished by transmitting 15 SYNC1 com-
mand bytes (0xFF hexadecimal), followed by one
SYNC0 command (0xFE hexadecimal). Once the
serial port of the ADC is in the command mode, the
user must reset all the internal logic by performing
a system reset sequence (see 2.3.2 System Reset
Sequence). After the converter is properly reset,
the configuration register bits should be configured
as appropriate, for example, the voltage reference
selection, word rate, signal polarity(unipolar or bi-
polar) should be configured.
Calibrations or conversions can then be performed
as appropriate.
2.12 PCB Layout
For optimal performance, the CS5530 should be
placed entirely over an analog ground plane. All
grounded pins on the ADC, including the DGND
pin, should be connected to the analog ground
plane that runs beneath the chip. In a split-plane
system, place the analog-digital plane split imme-
diately adjacent to the digital portion of the chip.
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| CDB5534U-Z | 功能描述:EVAL BD 24-BIT ADCS W/ULTRALN PG 制造商:cirrus logic inc. 系列:- 零件狀態(tài):在售 A/D 轉(zhuǎn)換器數(shù):1 位數(shù):24 采樣率（每秒）:3.84k 數(shù)據(jù)接口:串行 輸入范圍:±2.5 V 不同條件下的功率（典型值）:35mW @ 3.84kSPS 使用的 IC/零件:CS5534 所含物品:板，電纜 標(biāo)準(zhǔn)包裝:1 |
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