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參數(shù)資料
| 型號： | CDB5530U |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 18/36頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR CS5530 |
| 標準包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 3.84k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | ±2.5 V |
| 在以下條件下的電源（標準）： | 35mW @ 5V |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | CS5530 |
| 已供物品： | 板，CD |
| 相關(guān)產(chǎn)品： | CS5530-ISZR-ND - IC ADC 24BIT 1CH W/LNA 20-SSOP 598-1283-5-ND - IC ADC 24BIT 1CH W/LNA 20SSOP 598-1198-5-ND - IC DELTA-SIGMA 24BIT 1CH 20-SSOP |
| 其它名稱： | 598-1158 |
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CS5530
DS742F3
25
2.6 Using Multiple ADCs Synchronously
Some applications require synchronous data out-
puts from multiple ADCs converting different ana-
log channels. Multiple CS5530 devices can be
synchronized in a single system by using the fol-
lowing guidelines:
1) All of the ADCs in the system must be operated
from the same oscillator source.
2) All of the ADCs in the system must share com-
mon SCLK and SDI lines.
3) A software reset must be performed at the same
time for all of the ADCs after system power-up (by
selecting all of the ADCs using their respective CS
pins, and writing the reset sequence to all parts, us-
ing SDI and SCLK).
4) A start conversion command must be sent to all
of the ADCs in the system at the same time. The ±
8 clock cycles of ambiguity for the first conversion
(or for a single conversion) will be the same for all
ADCs, provided that they were all reset at the same
time.
5) Conversions can be obtained by monitoring
SDO on only one ADC, (bring CS high for all but
one part) and reading the data out of each part indi-
vidually, before the next conversion data words are
ready.
An example of a synchronous system using two
CS5530 devices is shown in Figure 12.
2.7 Conversion Output Coding
The CS5530 outputs 24-bit data conversion words.
To read a conversion word the user must read the
conversion data register. The conversion data reg-
ister is 32 bits long and outputs the conversions
MSB first. The last byte of the conversion data reg-
ister contains an overflow flag bit. The overrange
flag (OF) monitors to determine if a valid conver-
sion was performed.
The CS5530 output data conversions in binary for-
mat when operating in unipolar mode and in two's
complement when operating in bipolar mode. Ta-
ble 3 shows the code mapping for both unipolar and
bipolar modes. VFS in the tables refers to the posi-
tive full-scale voltage range of the converter in the
specified gain range, and -VFS refers to the nega-
tive full-scale voltage range of the converter. The
total differential input range (between AIN+ and
AIN-) is from 0 to VFS in unipolar mode, and from
-VFS to VFS in bipolar mode.
CLOCK
SOURCE
CS5530
SDO
SDI
SCLK
CS
OSC2
SDO
SDI
SCLK
CS
OSC2
μC
Figure 12. Synchronizing Multiple ADCs
Table 3. Output Coding
Unipolar Input
Voltage
Offset
Binary
Bipolar Input
Voltage
Two's
Complement
>(VFS-1.5 LSB) FFFFFF >(VFS-1.5 LSB)
7FFFFF
VFS-1.5 LSB
FFFFFF
------
FFFFFE
VFS-1.5 LSB
7FFFFF
------
7FFFFE
VFS/2-0.5 LSB 800000
------
7FFFFF
-0.5 LSB
000000
------
FFFFFF
+0.5 LSB
000001
------
000000
-VFS+0.5 LSB
800001
------
800000
<(+0.5 LSB)
000000 <(-VFS+0.5 LSB)
800000
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