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參數(shù)資料
| 型號： | BX80539T2400 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1830 MHz, MICROPROCESSOR, PBGA479 |
| 封裝： | MICRO, FCBGA-479 |
| 文件頁數(shù)： | 8/91頁 |
| 文件大小： | 2017K |
| 代理商： | BX80539T2400 |
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Low Power Features
16
Datasheet
2.1.2.5
Deep Sleep State
Deep Sleep state is a very low power state the processor can enter while maintaining
context. Deep Sleep state is entered by asserting the DPSLP# pin while in the Sleep
state. BCLK may be stopped during the Deep Sleep state for additional platform level
power savings. BCLK stop/restart timings on appropriate chipset-based platforms with
the CK410M clock chip are as follows:
Deep Sleep entry: the system clock chip may stop/tristate BCLK within 2 BCLKs of
DPSLP# assertion. It is permissible to leave BCLK running during Deep Sleep.
Deep Sleep exit: the system clock chip must drive BCLK to differential DC levels
within 2-3 ns of DPSLP# deassertion and start toggling BCLK within 10 BCLK
periods.
To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be re-
started after DPSLP# deassertion as described above. A period of 15 microseconds (to
allow for PLL stabilization) must occur before the processor can be considered to be in
the Sleep state. Once in the Sleep state, the SLP# pin must be deasserted to re-enter
the Stop-Grant state.
While in Deep Sleep state, the processor is incapable of responding to snoop
transactions or latching interrupt signals. No transitions of signals are allowed on the
FSB while the processor is in Deep Sleep state. When the processor is in Deep Sleep
state, it will not respond to interrupts or snoop transactions. Any transition on an input
signal before the processor has returned to Stop-Grant state will result in unpredictable
behavior.
2.1.2.6
Deeper Sleep State
The Deeper Sleep state is similar to the Deep Sleep state but reduces core voltage to
one of two lower levels. One lower core voltage level is achieved by entering the base
Deeper Sleep state. The Deeper Sleep state is entered through assertion of the
DPRSTP# pin while in the Deep Sleep state. The other lower core voltage level, the
lowest possible in the processor, is achieved by entering the Intel Enhanced Deeper
Sleep state of Deeper Sleep state. The Intel Enhanced Deeper Sleep state is entered
through assertion of the DPRSTP# pin while in the Deep Sleep only when the L2 cache
has been completely shut down. Refer to Section 2.1.2.6.1 and Section 2.1.2.6.2 for
further details on reducing the L2 cache and entering Intel Enhanced Deeper Sleep
state.
In response to entering Deeper Sleep, the processor will drive the VID code
corresponding to the Deeper Sleep core voltage on the VID[6:0] pins.
Exit from the Deeper Sleep state or Intel Enhanced Deeper Sleep state is initiated by
DPRSTP# deassertion when either core requests a core state other than C4 or either
core requests a processor performance state other than the lowest operating point.
2.1.2.6.1
Intel Enhanced Deeper Sleep State
Intel Enhanced Deeper Sleep state is a sub-state of Deeper Sleep that extends power
saving capabilities by allowing the processor to further reduce core voltage once the L2
cache has been reduced to zero ways and completely shut down. The following events
occur when the processor enters Intel Enhanced Deeper Sleep state:
The last core entering C4 issues a P_LVL4 I/O read or an MWAIT(C4) instruction
and then progressively reduces the L2 cache to zero.
The processor drives the VID code corresponding to the Intel Enhanced Deeper
Sleep state core voltage on the VID[6:0] pins.
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