參數(shù)資料
型號(hào): BX80539T2400
廠商: INTEL CORP
元件分類: 微控制器/微處理器
英文描述: 1830 MHz, MICROPROCESSOR, PBGA479
封裝: MICRO, FCBGA-479
文件頁(yè)數(shù): 6/91頁(yè)
文件大?。?/td> 2017K
代理商: BX80539T2400
Low Power Features
14
Datasheet
2.1.1.5
Core C3 State
Core C3 state is a very low power state the processor core can enter while maintaining
context. Individual cores of the Intel Core Duo processor and Intel Core Solo processor
can enter the C3 state by initiating a P_LVL3 I/O read to the P_BLK or an MWAIT(C3)
instruction. Before entering the C3 state, the processor core flushes the contents of its
L1 caches into the processor’s L2 cache. Except for the caches, the processor core
maintains all its architectural state in the C3 state. The Monitor remains armed if it is
configured. All of the clocks in the processor core are stopped in the C3 state.
Because the core’s caches are flushed the processor keeps the core in the C3 state
when the processor detects a snoop on the FSB or when the other core of the dual core
processor accesses cacheable memory. The processor core will transition to the C0
state upon the occurrence of a Monitor event, SMI#, INIT#, LINT[1:0] (NMI, INTR), or
FSB interrupt message. RESET# will cause the processor core to immediately initialize
itself.
2.1.1.6
Core C4 State
Individual cores of the Intel Core Duo processor and Intel Core Solo processor can
enter the C4 state by initiating a P_LVL4 I/O read to the P_BLK or an MWAIT(C4)
instruction. The processor core behavior in the C4 state is identical to the behavior in
the C3 state. The only difference is that if both processor cores are in C4, then the
central power management logic will request that the entire dual core processor enter
the Deeper Sleep package low power state (see Section 2.1.2.5). The single core
processor would be put into the Deeper Sleep State in C4 state if the low power state
coordination logic is enabled.
To enable the package level Intel Enhanced Deeper Sleep Low Voltage, Dynamic Cache
Sizing and Intel Enhanced Deeper Sleep state fields must be configured in the software
programmable MSR.
2.1.2
Package Low Power States
The package level low power states are applicable for the Intel Core Duo processor as
well as the Intel Core Solo processor. The package level low power states are described
2.1.2.1
Normal State
This is the normal operating state for the processor. The processor enters the Normal
state when at least one of its cores is in the C0, C1/AutoHALT, or C1/MWAIT state.
2.1.2.2
Stop-Grant State
When the STPCLK# pin is asserted, each core of the Intel Core Duo processor and Intel
Core Solo processor enters the Stop-Grant state within 20 bus clocks after the
response phase of the processor-issued Stop Grant Acknowledge special bus cycle.
Processor cores that are already in the C2, C3, or C4 state remain in their current low-
power state. When the STPCLK# pin is deasserted, each core returns to its previous
core low power state.
Since the AGTL+ signal pins receive power from the FSB, these pins should not be
driven (allowing the level to return to VCCP) for minimum power drawn by the
termination resistors in this state. In addition, all other input pins on the FSB should be
driven to the inactive state.
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