- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄223478 > BX80539T2400 (INTEL CORP) 1830 MHz, MICROPROCESSOR, PBGA479 PDF資料下載
參數(shù)資料
| 型號： | BX80539T2400 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1830 MHz, MICROPROCESSOR, PBGA479 |
| 封裝： | MICRO, FCBGA-479 |
| 文件頁數(shù)： | 44/91頁 |
| 文件大?。?/td> | 2017K |
| 代理商： | BX80539T2400 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁當(dāng)前第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁
Datasheet
49
Package Mechanical Specifications and Pin Information
4.3
Alphabetical Signals Reference
Table 17.
Signal Description (Sheet 1 of 9)
Name
Type
Description
A[31:3]#
Input/
Output
A[31:3]# (Address) define a 232-byte physical memory address
space. In sub-phase 1 of the address phase, these pins transmit the
address of a transaction. In sub-phase 2, these pins transmit
transaction type information. These signals must connect the
appropriate pins of both agents on the Intel Core Duo processor
and the Intel Core Solo processor FSB. A[31:3]# are source
synchronous signals and are latched into the receiving buffers by
ADSTB[1:0]#. Address signals are used as straps which are
sampled before RESET# is deasserted.
A20M#
Input
If A20M# (Address-20 Mask) is asserted, the processor masks
physical address bit 20 (A20#) before looking up a line in any
internal cache and before driving a read/write transaction on the
bus. Asserting A20M# emulates the 8086 processor's address
wrap-around at the 1-Mbyte boundary. Assertion of A20M# is only
supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition
of this signal following an Input/Output write instruction, it must be
valid along with the TRDY# assertion of the corresponding Input/
Output Write bus transaction.
ADS#
Input/
Output
ADS# (Address Strobe) is asserted to indicate the validity of the
transaction address on the A[31:3]# and REQ[4:0]# pins. All bus
agents observe the ADS# activation to begin parity checking,
protocol checking, address decode, internal snoop, or deferred
reply ID match operations associated with the new transaction.
ADSTB[1:0]#
Input/
Output
Address strobes are used to latch A[31:3]# and REQ[4:0]# on their
rising and falling edges. Strobes are associated with signals as
shown below.
BCLK[1:0]
Input
The differential pair BCLK (Bus Clock) determines the FSB
frequency. All FSB agents must receive these signals to drive their
outputs and latch their inputs.
All external timing parameters are specified with respect to the
rising edge of BCLK0 crossing VCROSS.
BNR#
Input/
Output
BNR# (Block Next Request) is used to assert a bus stall by any bus
agent who is unable to accept new bus transactions. During a bus
stall, the current bus owner cannot issue any new transactions.
Signals
Associated
Strobe
REQ[4:0]#, A[16:3]#
ADSTB[0]#
A[31:17]#
ADSTB[1]#
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BX80551PG3000FN | 32-BIT, 3000 MHz, MICROPROCESSOR, PBGA775 |
| BX805565130P | 64-BIT, MICROPROCESSOR, BGA771 |
| BX805573060 | 64-BIT, 2400 MHz, MICROPROCESSOR, CBGA775 |
| BX80562X3210SLACU | 64-BIT, 266 MHz, MICROPROCESSOR, PBGA775 |
| BX80616I5660SLBLV | 64-BIT, 133 MHz, MICROPROCESSOR, PBGA1156 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BX80539T2500 S L8VP | 制造商:Intel 功能描述:MPU Core? Duo Processor T2500 65nm 2GHz 1.05V 478-Pin Micro-FCPGA |
| BX80543JC1300G | 制造商:Intel 功能描述:ITANIUM 2 1.3GHZ 3M 400FSB - Boxed Product (Development Kits) |
| BX80543JC1600G | 制造商:Intel 功能描述:ITANIUM 2 1.6GHZ 3M 400FSB - Boxed Product (Development Kits) |
| BX80543KC1600K | 制造商:Intel 功能描述:ITANIUM 2 1.6GHZ 9M 400FSB - Boxed Product (Development Kits) |
| BX80546KF2833H | 制造商:Intel 功能描述:XEON MP 2.83GHZ 4MB 667FSB - Boxed Product (Development Kits) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。