
List of Figures
ix
21095B/0—June 1997
AMD-645 Peripheral Bus Controller Data Sheet
Preliminary Information
List of Figures
Figure 1-1.
Figure 2-1.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 5-6.
Figure 5-7.
Figure 5-8.
Figure 5-9.
Figure 5-10. ROM Cycle 32-Bit to 8-Bit Conversion . . . . . . . . . . . . . . . . 5-13
Figure 5-11. Configuration Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Figure 5-12. Configuration Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Figure 5-13. Subtractive Decode Timing . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
Figure 5-14. DMA Transfer Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20
Figure 5-15. ISA Bus Master Arbitration Timing . . . . . . . . . . . . . . . . . . 5-21
Figure 5-16. ISA Bus Master-to-PCI Memory (Memory Read) . . . . . . . . 5-22
Figure 5-17. ISA Bus Master-to-PCI Memory (Memory Write). . . . . . . . 5-22
Figure 5-18. Type F DMA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37
Figure 5-19. DMA Ready Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38
Figure 5-20. Ultra DMA-33 IDE Read Burst. . . . . . . . . . . . . . . . . . . . . . . 5-41
Figure 5-21. Pausing a DMA Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-42
Figure 5-22. Drive Terminating a DMA Read Burst . . . . . . . . . . . . . . . . 5-42
Figure 5-23. Host Terminating DMA Burst During Read Command. . . 5-43
Figure 5-24. Ultra DMA-33 IDE Write Burst . . . . . . . . . . . . . . . . . . . . . . 5-44
Figure 5-25. Drive Terminating DMA Burst During Write Command. . 5-45
Figure 5-26. Host Terminating DMA Burst During Write Command . . 5-45
Figure 5-27. PIO Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-57
Figure 5-28. IDE Multiword DMA Cycle . . . . . . . . . . . . . . . . . . . . . . . . . 5-58
Figure 7-1.
Strap Option Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27
Figure 9-1.
PCLK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
Figure 9-2.
Setup, Hold, and Valid Delay Timing Diagram . . . . . . . . . . 9-6
Figure 9-3.
ISA Master Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
Figure 9-4.
ISA 8-Bit Slave Interface Timing. . . . . . . . . . . . . . . . . . . . . 9-11
Figure 9-5.
ISA 16-Bit Slave Interface Timing. . . . . . . . . . . . . . . . . . . . 9-13
Figure 9-6.
ISA Master-to-PCI Access Timing . . . . . . . . . . . . . . . . . . . . 9-15
Figure 9-7.
Other ISA Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17
AMD-640 Chipset System Block Diagram. . . . . . . . . . . . . . . 1-4
AMD-645 Peripheral Bus Controller Block Diagram. . . . . . 2-8
I/O Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
I/O Cycle 16-Bit to 8-Bit Conversion . . . . . . . . . . . . . . . . . . . 5-5
Non-Posted PCI-to-ISA Access . . . . . . . . . . . . . . . . . . . . . . . . 5-6
Posted PCI-to-Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
ISA Bus Memory Access Cycle. . . . . . . . . . . . . . . . . . . . . . . . 5-8
ISA Bus Memory Cycle: 16-Bit to 8-Bit Conversion . . . . . . . 5-9
Memory Cycle 32-Bit to 8-Bit Conversion . . . . . . . . . . . . . . 5-10
Memory Cycle 32-Bit to 16-Bit Conversion . . . . . . . . . . . . . 5-11
ROM Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12