- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄366551 > AM79C978AVCW (ADVANCED MICRO DEVICES INC) Single-Chip 1/10 Mbps PCI Home Networking Controller PDF資料下載
參數(shù)資料
| 型號(hào)： | AM79C978AVCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | Single-Chip 1/10 Mbps PCI Home Networking Controller |
| 中文描述： | 5 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁(yè)數(shù)： | 81/256頁(yè) |
| 文件大?。?/td> | 3505K |
| 代理商： | AM79C978AVCW |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)當(dāng)前第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)第249頁(yè)第250頁(yè)第251頁(yè)第252頁(yè)第253頁(yè)第254頁(yè)第255頁(yè)第256頁(yè)
Am79C978A
81
Table 18.
MII Control Frame Format
The start field (ST) is followed by the operation field (OP).
The operation field (OP) indicates whether the operation
is a read or a write operation. This is followed by the PHY
address (PHYAD) and the register address (REGAD) that
was programed into BCR33 of the Fast Ethernet control-
ler. This field is followed by a bus turnaround field (TA).
During the read operation, the bus turnaround field is
used to determine if the PHY is responding properly to the
read request. The data field to/from the MAC controller is
then written to or read from BCR34. The final field is the
idle field, and it is required to allow the drivers to turn off.
The PHYADD field, which is five bits wide, allows 32
unique PHY addresses. The managed PHY layer device
that is connected to a station management entity via the
MII interface has to respond to transactions addressed to
the PHY
’
s address. A station management entity at-
tached to multiple PHYs is required to have prior knowl-
edge of the appropriate PHY address.
No SRAM Configuration
If the SRAM_SIZE (BCR25, bits 7-0) value is 0 in the
SRAM size register, the controller will assume that there
is no SRAM present and will reconfigure the four internal
FIFOs into two FIFOs, one for transmit and one for re-
ceive. The FIFOs will operate the same as in the PCnet-
PCI II controller. When the SRAM_SIZE (BCR25, bits 7-
0) value is 0, the SRAM_BND (BCR26, bits 7-0) are ig-
nored by the controller. See Figure 44.
Low Latency Receive Configuration
If the LOLATRX (BCR27, bit 4) bit is set to 1, then the con-
troller will configure itself for a low latency receive config-
uration. In this mode, SRAM is required at all times. If the
SRAM_SIZE (BCR25, bits 7-0) value is 0, the controller
will not configure for low latency receive mode. The con-
troller will provide a fast path on the receive side bypass-
ing the SRAM. All transmit traffic will go to the SRAM, so
SRAM_BND (BCR26, bits 7-0) has no meaning in low la-
tency receive mode. When the controller has received 16
bytes from the network, it will start a DMA request to the
PCI Bus Interface Unit. The controller will not wait for the
first 64 bytes to pass to check for collisions in Low Latency
Receive mode. The controller must be in STOP before
switching to this mode. See Figure 45.
CAUTION:
To provide data integrity when switching into
and out of the low latency mode, DO NOT SET the
FASTSPNDE bit when setting the SPND bit. Receive
frames WILL be overwritten and the controller may give
erratic behavior when it is enabled again.
Direct SRAM Access
The SRAM can be accessed through the Expansion Bus
Data port (BCR30). To access this data port, the user
must load the upper address EPADDRU (BCR29, bits 3-
0) and set FLASH (BCR29, bit 15) to 0. Then the user will
load the lower 16 bits of address EPADDRL (BCR28, bits
15-0). To initiate a read, the user reads the Expansion Bus
Data Port (BCR30). This slave access from the PCI will
result in a retry for the very first access. Subsequent ac-
cesses may give a retry or not, depending on whether or
not the data is present and valid. The direct SRAM access
uses the same FLASH/EPROM access except for ac-
cessing the SRAM in word format instead of byte format.
This access is meant to be a diagnostic access only. The
SRAM can only be accessed while the controller is in
STOP or SPND (FASTSPNDE is set to 0) mode.
PRE
ST
OP
PHYAD
REGAD
TA
DATA
IDLE
READ
1.1
01
10
AAAAA
RRRRR
Z0
D31
………
D0
Z
WRITE
1.1
01
01
AAAAA
RRRRR
10
D31
………
D0
Z
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C978 | Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C981 | Integrated Multiport Repeater Plus⑩ (IMR+⑩) |
| AM79C981JC | Integrated Multiport Repeater Plus⑩ (IMR+⑩) |
| AM79C982 | basic Integrated Multiport Repeater (bIMR) |
| AM79C982-4JC | basic Integrated Multiport Repeater (bIMR) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C978KC/W | 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C978VC/W | 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C979BKC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C98 | 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:Twisted-Pair Ethernet Transceiver (TPEX) |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。