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| 型號(hào)： | AM79C978AVCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Single-Chip 1/10 Mbps PCI Home Networking Controller |
| 中文描述： | 5 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁(yè)數(shù)： | 237/256頁(yè) |
| 文件大?。?/td> | 3505K |
| 代理商： | AM79C978AVCW |
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APPENDIX B
B-1
Am79C978A
Look-Ahead Packet Processing
(LAPP) Concept
INTRODUCTION
A driver for the controller would normally require that
the CPU copy receive frame data from the controllers
buffer space to the applications buffer space after the
entire frame has been received by the controller. For
applications that use a ping-pong windowing style, the
traffic on the network will be halted until the current
frame has been completely processed by the entire ap-
plication stack. This means that the time between last
byte of a receive frame arriving at the client
’
s Ethernet
controller and the client
’
of the next outgoing frame will be separated by:
1. The time that it takes the client
’
s CPU interrupt pro-
cedure to pass software control from the current
task to the driver,
2. Plus the time that it takes the client driver to pass
the header data to the application and request an
application buffer,
3. Plus the time that it takes the application to gener-
ate the buffer pointer and then return the buffer
pointer to the driver,
4. Plus the time that it takes the client driver to transfer
all of the frame data from the controller
’
s buffer space
into the application
’
s buffer space and then call the
application again to process the complete frame,
5. Plus the time that it takes the application to process
the frame and generate the next outgoing frame, end
6. Plus the time that it takes the client driver to set up
the descriptor for the controller and then write a
TDMD bit to CSR0.
The sum of these times can often be about the same
as the time taken to actually transmit the frames on the
wire, thereby, yielding a network utilization rate of less
than 50 percent.
An important thing to note is that the controller
’
s data
transfers to its buffer space are such that the system
bus is needed by the controller for approximately 4
percent of the time. This leaves 96 percent of the
system bus bandwidth for the CPU to perform some
of the interframe operations in advance of the com-
pletion of network receive activity, if possible. The
question then becomes: how much of the tasks that
need to be performed between reception of a frame
and transmission of the next frame can be performed
before the reception of the frame actually ends at the
network, and how can the CPU be instructed to per-
form these tasks during the network reception time
The answer depends upon exactly what is happening
in the driver and application code, but the steps that
can be performed at the same time as the receive
data are arriving include as much as the first three
steps and part of the fourth step shown in the se-
quence above. By performing these steps before the
entire frame has arrived, the frame throughput can be
substantially increased.
A good increase in performance can be expected when
the first three steps are performed before the end of the
network receive operation. A much more significant
performance increase could be realized if the controller
could place the frame data directly into the applica-
tion
’
s buffer space; (i.e., eliminate the need for step 4.)
In order to make this work, it is necessary that the ap-
plication buffer pointer be determined before the frame
has completely arrived, then the buffer pointer in the
next descriptor for the receive frame would need to be
modified in order to direct the controller to write directly
to the application buffer. More details on this operation
will be given later.
An alternative modification to the existing system can
gain a smaller but still significant improvement in per-
formance. This alternative leaves Step 4 unchanged in
that the CPU is still required to perform the copy oper-
ation, but is allows a large portion of the copy operation
to be done before the frame has been completely re-
ceived by the controller, i.e., the CPU can perform the
copy operation of the receive data from the controller
’
s
buffer space into the application buffer space before
the frame data has completely arrived from the net-
work. This allows the copy operation of Step 4 to be
performed concurrently with the arrival of network data,
rather than sequentially, following the end of network
receive activity.
OUTLINE OF LAPP FLOW
This section gives a suggested outline for a driver that
utilizes the LAPP feature of the controller.
Note:
The labels in the following text are used as refer-
ences in the timeline diagram that follows (Figure B-1).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C978 | Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C981 | Integrated Multiport Repeater Plus⑩ (IMR+⑩) |
| AM79C981JC | Integrated Multiport Repeater Plus⑩ (IMR+⑩) |
| AM79C982 | basic Integrated Multiport Repeater (bIMR) |
| AM79C982-4JC | basic Integrated Multiport Repeater (bIMR) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C978KC/W | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C978VC/W | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C979BKC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C98 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Twisted-Pair Ethernet Transceiver (TPEX) |
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