
156
Am79C978A
This bit is read accessible al-
ways, write accessible only when
either the STOP or the SPND bit
is set. EXTREQ is cleared by
H_RESET and is not affected by
S_RESET or STOP.
7
DWIO
Double Word I/O. When set, this
bit indicates that the Am79C978A
controller is programmed for
DWord I/O (DWIO) mode. When
cleared, this bit indicates that the
Am79C978A controller is pro-
grammed for Word I/O (WIO)
mode. This bit affects the I/O Re-
source Offset map and it affects
the
defined
Am79C978A controller
’
s I/O re-
sources. See the DWIO and WIO
sections for more details.
width
of
the
The initial value of the DWIO bit is
determined by the programming
of the EEPROM.
The value of DWIO can be al-
tered
automatically
Am79C978A controller. Specifi-
cally, the Am79C978A controller
will set DWIO if it detects a
DWord write access to offset 10h
from the Am79C978A controller
’
s
I/O base address (corresponding
to the RDP resource).
by
the
Once the DWIO bit has been set
to a 1, only a H_RESET or an EE-
PROM read can reset it to a 0.
(Note that the EEPROM read op-
eration will only set DWIO to a 0 if
the appropriate bit inside of the
EEPROM is set to 0.)
This bit is read accessible al-
ways. DWIO is read only, write
operations have no effect. DWIO
is cleared by H_RESET and is
not affected S_RESET or by set-
ting the STOP bit.
6
BREADE
Burst Read Enable. When
set, this bit enables burst
mode during memory read
accesses. When cleared,
this bit prevents the device
from performing bursting
during read accesses. The
Am79C978A controller can
perform
burst
when reading the initializa-
tion block, the descriptor
ring
entries
SWSTYLE = 3),
buffer memory.
transfers
(when
the
and
BREADE should be set to 1
when the Am79C978A control-
ler is used in a PCI bus applica-
tion to guarantee maximum
performance.
This bit is read accessible al-
ways; write accessible only when
either the STOP or the SPND bit
is set. BREADE is cleared by
H_RESET and is not affected by
S_RESET or STOP.
5
BWRITE
Burst Write Enable. When set,
this bit enables burst mode during
memory write accesses. When
cleared, this bit prevents the de-
vice from performing bursting
during
write
accesses.
Am79C978A controller can per-
form burst transfers when writing
the descriptor ring entries (when
SWSTYLE = 3), and the buffer
memory.
The
BWRITE should be set to 1
when the Am79C978A control-
ler is used in a PCI bus applica-
tion to guarantee maximum
performance.
This bit is read accessible al-
ways, write accessible only when
either the STOP or the SPND bit
is set. BWRITE is cleared by
H_RESET and is not affected by
S_RESET or STOP.
4-3
PHYSEL[1:0] PHYSEL[1:0] bits allow for soft-
ware controlled selection of differ-
ent operation and test modes. The
normal mode of operation is when
both bits 0 and 1 are set to 0 to se-
lect the Expansion ROM/Flash.
Setting bit 0 to 1 and bit 1 to 0 al-
lows snooping of the internal MII-
compatible bus to allow External
Address
(EADI). See Table 38 for details.
Detection
Interface