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參數(shù)資料
| 型號： | AM79C978AVCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Single-Chip 1/10 Mbps PCI Home Networking Controller |
| 中文描述： | 5 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁數(shù)： | 71/256頁 |
| 文件大?。?/td> | 3505K |
| 代理商： | AM79C978AVCW |
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Am79C978A
71
In internal loopback operation, the Am79C978A con-
troller provides a special mode to test the collision
logic. When FCOLL (CSR15, bit 4) is set to 1, a colli-
sion is forced during every transmission attempt. This
will result in a Retry error.
Full-Duplex Operation
The Am79C978A controller supports full-duplex
operation on the 10BASE-T and MII interfaces.
Full-duplex operation allows simultaneous transmit
and receive activity. Full-duplex operation is en-
abled by the FDEN bit located in BCR9. Full-duplex
operation is also enabled through Auto-Negotiation
when DANAS (BCR 32, bit 7) is not enabled and
the ASEL bit is set, and its link partner is capable
of Auto-Negotiation and full-duplex operation.
When operating in full-duplex mode, the following
changes to the device operation are made:
Bus Interface/Buffer Management Unit changes:
The first 64 bytes of every transmit frame are not
preserved in the Transmit FIFO during transmission
of the first 512 bits as described in the
Transmit Ex-
ception Conditions
section. Instead, when full-du-
plex mode is active and a frame is being transmitted,
the XMTFW bits (CSR80, bits 9-8) always
govern
when transmit DMA is requested.
Successful reception of the first 64 bytes of every
receive frame is not a requirement for Receive DMA
to begin as described in the
Receive Exception Con-
ditions
section. Instead, receive DMA will be re-
quested as soon as either the RCVFW threshold
(CSR80, bits 12-13) is reached or a complete valid
receive frame is detected, regardless of length. This
Receive FIFO operation is identical to when the RPA
bit (CSR124, bit 3) is set during half-duplex mode
operation.
The MAC engine changes for full-duplex operation are
as follows:
Changes to the transmit deferral mechanism:
—
Transmission is not deferred while receive is active.
—
The IPG counter which governs transmit de-
ferral during the IPG between back-to-back
transmits is started when transmit activity for
the first packet ends, instead of when transmit
and carrier activity ends.
The 4.0 μs carrier sense blinding period after a
transmission during which the SQE test normally
occurs is disabled.
The collision indication input to the MAC engine is
ignored.
The internal PHY changes for full-duplex operation are
as follows:
The collision detect (COL) pin is disabled.
The SQE test function is disabled.
Loss of Carrier (LCAR) reporting is disabled.
PHY Control Register (TBR0) bit 8 is set to 1 if Auto-
Negotiation is disabled.
Full-Duplex Link Status LED Support
The Am79C978A controller provides bits in each of the
LED Status registers (BCR4, BCR5, BCR6, BCR7, and
BCR48) to display the Full-Duplex Link Status. If the
FDLSE bit (bit 8) is set, a value of 1 will be sent to the
associated LEDOUT bit when in Full-Duplex.
PHY/MAC Interface
The internal MII-compatible interface provides the data
path connection between the 10BASE-T PHY, the 1 Mbps
HomePNA PHY, and the 10/100 Media Access Controller
(MAC). The interface is compatible with Clause 22 of the
IEEE 802.3 standard specification.
10BASE-T Physical Layer
The 10BASE-T block consists of the following sub-blocks:
—
Transmit Process
—
Receive Process
—
Interface Status
—
Collision Detect Function
—
Jabber Function
—
Reverse Polarity Detect
Refer to Figure 37 for the 10BASE-T block diagram.
Twisted Pair Transmit Function
Data transmission over the 10BASE-T medium re-
quires use of the integrated 10BASE-T MAU and uses
the differential driver circuitry on the TX± pins.
TX± is a differential twisted-pair driver. When properly
terminated, TX± will meet the transmitter electrical re-
quirements for 10BASE-T transmitters as specified in
IEEE 802.3, Section 14.3.1.2. The load is a twisted pair
cable that meets IEEE 802.3, Section 14.4.
The TX± signal is filtered on the chip to reduce har-
monic content per Section 14.3.2.1 (10BASE-T). Since
filtering is performed in silicon, TX± can be connected
directly to a standard transformer. External filtering
modules are not needed.
Twisted Pair Receive Function
The RX+ port is a differential twisted-pair receiver.
When properly terminated, the RX+ port will meet the
electrical requirements for 10BASE-T receivers as
specified in IEEE 802.3, Section 14.3.1.3. The receiver
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| AM79C978 | Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C981 | Integrated Multiport Repeater Plus⑩ (IMR+⑩) |
| AM79C981JC | Integrated Multiport Repeater Plus⑩ (IMR+⑩) |
| AM79C982 | basic Integrated Multiport Repeater (bIMR) |
| AM79C982-4JC | basic Integrated Multiport Repeater (bIMR) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C978KC/W | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C978VC/W | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C979BKC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C98 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Twisted-Pair Ethernet Transceiver (TPEX) |
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