- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366551 > AM79C978AVCW (ADVANCED MICRO DEVICES INC) Single-Chip 1/10 Mbps PCI Home Networking Controller PDF資料下載
參數(shù)資料
| 型號(hào)： | AM79C978AVCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Single-Chip 1/10 Mbps PCI Home Networking Controller |
| 中文描述： | 5 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁(yè)數(shù)： | 64/256頁(yè) |
| 文件大小： | 3505K |
| 代理商： | AM79C978AVCW |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)當(dāng)前第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)第249頁(yè)第250頁(yè)第251頁(yè)第252頁(yè)第253頁(yè)第254頁(yè)第255頁(yè)第256頁(yè)
64
Am79C978A
Counters are provided to report the Receive Collision
Count and Runt Packet Count for network statistics
and utilization calculations.
Media Access Management
The basic requirement for all stations on the network is
to provide fairness of channel allocation. The IEEE
802.3/Ethernet protocols define a media access mech-
anism which permits all stations to access the channel
with equality. Any node can attempt to contend for the
channel by waiting for a predetermined time (Inter
Packet Gap) after the last activity, before transmitting
on the media. The channel is a multidrop communica-
tions media (with various topological configurations
permitted), which allows a single station to transmit and
all other stations to receive. If two nodes simulta-
neously contend for the channel, their signals will inter-
act causing loss of data, defined as a collision. It is the
responsibility of the MAC to attempt to avoid and
recover from a collision and to guarantee data integrity
for the end-to-end transmission to the receiving station.
Medium Allocation
The IEEE/ANSI 802.3 standard (ISO/IEC 8802-3 1990)
requires that the CSMA/CD MAC monitor the medium
for traffic by watching for carrier activity. When carrier
is detected, the media is considered busy, and the
MAC should defer to the existing message.
The ISO 8802-3 (IEEE/ANSI 802.3) standard also
allows optionally a two-part deferral after a receive
message.
See ANSI/IEEE Std 802.3-1993 Edition, 4.2.3.2.1:
Note:
“It is possible for the PLS carrier sense indica-
tion to fail to be asserted during a collision on the me-
dia. If the deference process simply times the inter-
frame gap based on this indication, it is possible for a
short interframe gap to be generated, leading to a po-
tential reception failure of a subsequent frame. To en-
hance system robustness, the following optional
measures (as specified in 4.2.8) are recommended
when InterFrameSpacingPart1 is other than 0:
1. Upon completing a transmission, start timing the in-
terrupted gap as soon as transmitting and carrier
sense are both false.
2. When timing an inter-frame gap following reception,
reset the inter-frame gap timing if carrier sense be-
comes true during the first 2/3 of the inter-frame gap
timing interval. During the final 1/3 of the interval,
the timer shall not be reset to ensure fair access to
the medium. An initial period shorter than 2/3 of the
interval is permissible including 0.”
The MAC engine implements the optional receive two-
part deferral algorithm, with an InterFrameSpacing-
Part1 time of 6.0 ms. The InterFrameSpacingPart 2 in-
terval is, therefore, 3.4 ms.
TheAm79C978A controller will perform the two-part
deferral algorithm as specified in the
Process Defer-
ence
section. The Inter Packet Gap (IPG) timer will
start timing the 9.6 ms InterFrameSpacing after the
receive carrier is deasserted. During the first part de-
ferral (InterFrameSpacingPart1 - IFS1), the
Am79C978A controller will defer any pending trans-
mit frame and respond to the receive message. The
IPG counter will be cleared to 0 continuously until the
carrier deasserts, at which point the IPG counter will
resume the 9.6 ms count once again. Once the IFS1
period of 6.0 ms has elapsed, the Am79C978A con-
troller will begin timing the second part deferral
(InterFrameSpacingPart2 - IFS2) of 3.4 ms. Once
IFS1 has completed and IFS2 has commenced, the
Am79C978A controller will not defer to a receive
frame if a transmit frame is pending. This means that
the Am79C978A controller will not attempt to receive
the receive frame, since it will start to transmit and
generate a collision at 9.6 ms. TheAm79C978A con-
troller will complete the preamble (64-bit) and jam
(32-bit) sequence before ceasing transmission and
invoking the random backoff algorithm.
TheAm79C978A controller allows the user to pro-
gram the IPG and the first-part deferral
(InterFrameSpacingPart1 - IFS1) through CSR125.
By changing the IPG default value of 96 bit times
(60h), the user can adjust the fairness or aggressive-
ness of the MAC on the network. By programming a
lower number of bit times than the ISO/IEC 8802-3
standard requires, the MAC engine will become
more aggressive on the network. This aggressive
nature will give rise to the Am79C978A controller
possibly capturing the network at times by forcing
other less aggressive compliant nodes to defer. By
programming a larger number of bit times, the MAC
will become less aggressive on the network and may
defer more often than normal. The performance of
the Am79C978A controller may decrease as the IPG
value is increased from the default value, but the re-
sulting behavior may improve network performance
by reducing collisions. TheAm79C978A controller
uses the same IPG for back-to-back transmits and
receive-to-transmit accesses. Changing IFS1 will
alter the period for which the MAC engine will defer
to incoming receive frames.
CAUTION: Care must be exercised when altering
these parameters
.
Adverse network activity could
result!
This transmit two-part deferral algorithm is imple-
mented as an option which can be disabled using the
DXMT2PD bit in CSR3. The IFS1 programming will
have no effect when DXMT2PD is set to 1, but the IPG
programming value is still valid. Two part deferral after
transmission is useful for ensuring that severe IPG
shrinkage cannot occur in specific circumstances,
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C978 | Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C981 | Integrated Multiport Repeater Plus⑩ (IMR+⑩) |
| AM79C981JC | Integrated Multiport Repeater Plus⑩ (IMR+⑩) |
| AM79C982 | basic Integrated Multiport Repeater (bIMR) |
| AM79C982-4JC | basic Integrated Multiport Repeater (bIMR) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C978KC/W | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C978VC/W | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C979BKC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C98 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Twisted-Pair Ethernet Transceiver (TPEX) |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。