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參數(shù)資料
| 型號： | AM79C978AVCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Single-Chip 1/10 Mbps PCI Home Networking Controller |
| 中文描述： | 5 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁數(shù)： | 54/256頁 |
| 文件大?。?/td> | 3505K |
| 代理商： | AM79C978AVCW |
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54
Am79C978A
Table 10.
Descriptor Write Sequence
FIFO DMA Transfers
The Am79C978A microcode will determine when a
FIFO DMA transfer is required. This transfer mode will
be used for transfers of data to and from the FIFOs.
Once the BIU has been granted bus mastership, it will
perform a series of consecutive transfer cycles before
relinquishing the bus. All transfers within the master
cycle will be either read or write cycles, and all transfers
will be to contiguous, ascending addresses. Both non-
burst and burst cycles are used, with burst mode being
the preferred mode when the device is used in a PCI
bus application.
Non-Burst FIFO DMA Transfers
In the default mode, the Am79C978A controller uses
non-burst transfers to read and write data when ac-
cessing the FIFOs. Each non-burst transfer will be per-
formed sequentially with the issue of an address and
the transfer of the corresponding data with appropriate
output signals to indicate selection of the active data
bytes during the transfer.
FRAME will be deasserted after every address phase.
Several factors will affect the length of the bus mastership
period. The possibilities are as follows:
Bus cycles will continue until the transmit FIFO is filled
to its high threshold (read transfers) or the receive
FIFO is emptied to its low threshold (write transfers).
The exact number of total transfer cycles in the bus
mastership period is dependent on all of the following
variables: the settings of the FIFO watermarks, the
conditions of the FIFOs, the latency of the system bus
to the Am79C978A controller
’
s bus request, the
speed of bus operation and bus preemption events.
The TRDY response time of the memory device will
also affect the number of transfers, since the speed of
the accesses will affect the state of the FIFO. During
accesses, the FIFO may be filling or emptying on the
network end. For example, on a receive operation, a
slower TRDY response will allow additional data to
accumulate inside of the FIFO. If the accesses are
slow enough, a complete DWord may become avail-
able before the end of the bus mastership period and,
thereby, increase the number of transfers in that pe-
riod. The general rule is that the longer the Bus Grant
latency, the slower the bus transfer operations; the
slower the clock speed, the higher the transmit water-
mark; or the higher the receive watermark, the longer
the bus mastership period will be.
Note:
The PCI Latency Timer is not significant during
non-burst transfers.
Burst FIFO DMA Transfers
Bursting is only performed by the Am79C978A con-
troller if the BREADE and/or BWRITE bits of BCR18
are set. These bits individually enable/disable the
ability of the Am79C978A controller to perform burst
accesses during master read operations and master
write operations, respectively.
A burst transaction will start with an address phase,
followed by one or more data phases. AD[1:0] will
always be 0 during the address phase indicating a
linear burst order.
During FIFO DMA read operations, all byte lanes will
always be active. TheAm79C978A controller will inter-
nally discard unused bytes. During the first and the last
data phases of a FIFO DMA burst write operation, one
or more of the byte enable signals may be inactive. All
other data phases will always write a complete DWord.
Figure 31 shows the beginning of a FIFO DMA write
with the beginning of the buffer not aligned to a DWord
boundary. TheAm79C978A controller starts off by writ-
ing only three bytes during the first data phase. This op-
eration aligns the address for all other data transfers to
a 32-bit boundary so that the Am79C978A controller
can continue bursting full DWords.
If a receive buffer does not end on a DWord boundary,
the Am79C978A controller will perform a non-DWord
write on the last transfer to the buffer. Figure 32 shows
the final three FIFO DMA transfers to a receive buffer.
Since there were only nine bytes of space left in the re-
ceive buffer, the Am79C978A controller bursts three
data phases. The first two data phases write a full
DWord, the last one only writes a single byte.
SWSTYLE
BCR20[7:0]
BWRITE
BCR18[5]
AD Bus Sequence
0
X
Address = XXXX XX04h
Data = MD2[15:0],
MD1[15:0]
Idle
Address = XXXX XX00h
Data = MD1[31:24]
2
X
Address = XXXX XX08h
Data = MD2[31:0]
Idle
Address = XXXX XX04h
Data = MD1[31:16]
3
0
Address = XXXX XX00h
Data = MD2[31:0]
Idle
Address = XXXX XX04h
Data = MD1[31:16]
3
1
Address = XXXX XX00h
Data = MD2[31:0]
Data = MD1[31:16]
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| AM79C981 | Integrated Multiport Repeater Plus⑩ (IMR+⑩) |
| AM79C981JC | Integrated Multiport Repeater Plus⑩ (IMR+⑩) |
| AM79C982 | basic Integrated Multiport Repeater (bIMR) |
| AM79C982-4JC | basic Integrated Multiport Repeater (bIMR) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C978KC/W | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C978VC/W | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C979BKC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C98 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Twisted-Pair Ethernet Transceiver (TPEX) |
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