參數(shù)資料
型號: AM79C978AVCW
廠商: ADVANCED MICRO DEVICES INC
元件分類: 微控制器/微處理器
英文描述: Single-Chip 1/10 Mbps PCI Home Networking Controller
中文描述: 5 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝: TQFP-144
文件頁數(shù): 202/256頁
文件大?。?/td> 3505K
代理商: AM79C978AVCW
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁當前第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁第242頁第243頁第244頁第245頁第246頁第247頁第248頁第249頁第250頁第251頁第252頁第253頁第254頁第255頁第256頁
202
Am79C978A
25
STP
Start of Packet indicates that this
is the first buffer to be used by the
Am79C978A controller for this
frame. It is used for data chaining
buffers. The STP bit must be set
in the first buffer of the frame, or
the Am79C978A controller will
skip over the descriptor and poll
the next descriptor(s) until the
OWN and STP bits are set. STP
is set by the host and is not
changed by the Am79C978A
controller.
24
ENP
End of Packet. End of Packet in-
dicates that this is the last buffer
to be used by the Am79C978A
controller for this frame. It is used
for data chaining buffers. If both
STP and ENP are set, the frame
fits into one buffer and there is no
data chaining. ENP is set by the
host and is not changed by the
Am79C978A controller.
23
BPE
Bus Parity Error is set by the
Am79C978A controller when a
parity error occurred on the bus
interface during a data transfers
from the transmit buffer associat-
ed with this descriptor. The
Am79C978A controller will only
set BPE when the advanced par-
ity error handling is enabled by
setting APERREN (BCR20, bit
10) to 1. BPE is set by the
Am79C978A
controller
cleared by the host.
and
This bit does not exist, when
the Am79C978A controller is
programmed to use 16-bit soft-
ware structures for the descrip-
tor ring entries (BCR20, bits 7-
0, SWSTYLE is cleared to 0).
22-16 RES
Reserved locations.
15-12 ONES
These four bits must be written as
ones. This field is written by the
host and unchanged by the
Am79C978A controller.
11-00 BCNT
Buffer Byte Count is the usable
length of the buffer pointed to by
this descriptor, expressed as the
two
s complement of the length of
the buffer. This is the number of
bytes from this buffer that will be
transmitted by the Am79C978A
controller. This field is written by
the host and is not changed by
the
Am79C978A
There are no minimum buffer size
restrictions.
controller.
TMD2
Bit
Name
Description
31
BUFF
Buffer error is set by the
Am79C978A controller during
transmission
Am79C978A controller does not
find the ENP flag in the current
descriptor and does not own the
next descriptor. This can occur in
either of two ways:
when
the
1. The OWN bit of the next buffer
is 0.
2. FIFO underflow occurred be-
fore the Am79C978A controller
obtained
the
(TMD1[31:24]) of the next de-
scriptor. BUFF is set by the
Am79C978A
controller
cleared by the host.
STATUS
byte
and
If a Buffer Error occurs, an Under-
flow Error will also occur. BUFF is
set by the Am79C978A controller
and cleared by the host.
30
UFLO
Underflow error indicates that the
transmitter has truncated a mes-
sage because it could not read
data from memory fast enough.
UFLO indicates that the FIFO has
emptied before the end of the
frame was reached.
When DXSUFLO (CSR3, bit 6) is
cleared to 0, the transmitter is
turned off when an UFLO error
occurs (CSR0, TXON = 0).
When DXSUFLO is set to 1, the
Am79C978A controller grace-
fully recovers from an UFLO er-
ror. It scans the transmit
descriptor ring until it finds the
start of a new frame and starts a
new transmission.
UFLO is set by the Am79C978A
controller and cleared by the host.
相關PDF資料
PDF描述
AM79C978 Single-Chip 1/10 Mbps PCI Home Networking Controller
AM79C981 Integrated Multiport Repeater Plus⑩ (IMR+⑩)
AM79C981JC Integrated Multiport Repeater Plus⑩ (IMR+⑩)
AM79C982 basic Integrated Multiport Repeater (bIMR)
AM79C982-4JC basic Integrated Multiport Repeater (bIMR)
相關代理商/技術參數(shù)
參數(shù)描述
AM79C978KC/W 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller
AM79C978VC/W 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller
AM79C979BKC\\W 制造商:Advanced Micro Devices 功能描述:
AM79C98 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Twisted-Pair Ethernet Transceiver (TPEX)