- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366551 > AM79C978AVCW (ADVANCED MICRO DEVICES INC) Single-Chip 1/10 Mbps PCI Home Networking Controller PDF資料下載
參數(shù)資料
| 型號： | AM79C978AVCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Single-Chip 1/10 Mbps PCI Home Networking Controller |
| 中文描述： | 5 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁數(shù)： | 30/256頁 |
| 文件大?。?/td> | 3505K |
| 代理商： | AM79C978AVCW |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁當(dāng)前第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁第242頁第243頁第244頁第245頁第246頁第247頁第248頁第249頁第250頁第251頁第252頁第253頁第254頁第255頁第256頁
30
Am79C978A
Figure 1.
Media Independent Interface
MII Receive Interface
The MII receive clock is also generated by the external
PHY and is sent to the Am79C978A controller on the
RX_CLK input pin. The clock will be the same fre-
quency as the TX_CLK but will be out of phase and can
run at 25 MHz or 2.5 MHz, depending on the speed of
the network to which the external PHY is attached.
The RX_CLK is a continuous clock during the reception
of the frame, but can be stopped for up to two RX_CLK
periods at the beginning and the end of frames, so that
the external PHY can sync up to the network data traffic
necessary to recover the receive clock. During this
time, the external PHY may switch to the TX_CLK to
maintain a stable clock on the receive interface. The
Am79C978A controller will handle this situation with no
loss of data. The data is a nibble-wide (4 bits) data
path, RXD(3:0), from the external PHY to the
Am79C978A controller and is synchronous to the rising
edge of RX_CLK.
The receive process starts when RX_DV is asserted.
RX_DV will remain asserted until the end of the receive
frame. The Am79C978A controller requires CRS (Carrier
Sense) to toggle in between frames in order to receive
them properly. Errors in the currently received frame are
signaled across the MII by the RX_ER pin. RX_ER can be
used to signal special conditions
out of band
when RX_DV
is not asserted. Two defined out-of-band conditions for this
are the 100BASE-TX signaling of
bad
Start of Frame De-
limiter and the 100BASE-T4 indication of illegal code group
before the receiver has
synched
to the incoming data. The
Am79C978A controller will not respond to these condi-
tions. All
out of band
conditions are currently treated as
NULL events. Certain
in band
non-IEEE 802.3u-compliant
flow control sequences may cause erratic behavior for the
Am79C978A controller.
MII Network Status Interface
The MII also provides signals that are consistent and
necessary for IEEE 802.3 and IEEE 802.3u operation.
These signals are CRS (Carrier Sense) and COL (Col-
lision Sense). Carrier Sense is used to detect non-idle
activity on the network. Collision Sense is used to indi-
cate that simultaneous transmission has occurred in a
half-duplex network.
MII Management Interface
The MII provides a two-wire management interface so
that the Am79C978A controller can control and receive
status from external PHY devices.
The Network Port Manager copies the PHYAD after
the Am79C978A controller reads the EEPROM and
uses it to communicate with the external PHY. The
PHY address must be programmed into the EEPROM
prior to starting the Am79C978A controller. This is
necessary so that the internal management controller
can work autonomously from the software driver and
can always know where to access the external PHY.
The Am79C978A controller is unique by offering di-
rect hardware support of the external PHY device
without software support. The PHY address of 1Fh is
reserved and should not be used. To access the ex-
ternal PHYs, the software driver must have knowl-
edge of the external PHY
’
s address when multiple
PHYs are present before attempting to address it.
The MII Management Interface uses the MII Control, Ad-
dress, and Data registers (BCR32, 33, 34) to control and
communicate to the external PHYs. The Am79C978A
controller generates MII management frames to the ex-
ternal PHY through the MDIO pin synchronous to the ris-
ing edge of the Management Data Clock (MDC) based on
a combination of writes and reads to these registers.
4
RXD(3:0)
RX_DV
RX_ER
RX_CLK
CRS
4
TXD(3:0)
TX_EN
Am79C978A
M
COL
Receive Signals
Transmit Signals
Management Port Signals
Network Status Signals
TX_CLK
MDIO
MDC
22399A-4
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C978 | Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C981 | Integrated Multiport Repeater Plus⑩ (IMR+⑩) |
| AM79C981JC | Integrated Multiport Repeater Plus⑩ (IMR+⑩) |
| AM79C982 | basic Integrated Multiport Repeater (bIMR) |
| AM79C982-4JC | basic Integrated Multiport Repeater (bIMR) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C978KC/W | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C978VC/W | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C979BKC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C98 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Twisted-Pair Ethernet Transceiver (TPEX) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。