- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366551 > AM79C978AVCW (ADVANCED MICRO DEVICES INC) Single-Chip 1/10 Mbps PCI Home Networking Controller PDF資料下載
參數(shù)資料
| 型號： | AM79C978AVCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Single-Chip 1/10 Mbps PCI Home Networking Controller |
| 中文描述： | 5 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁數(shù)： | 49/256頁 |
| 文件大?。?/td> | 3505K |
| 代理商： | AM79C978AVCW |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁當前第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁第242頁第243頁第244頁第245頁第246頁第247頁第248頁第249頁第250頁第251頁第252頁第253頁第254頁第255頁第256頁
Am79C978A
49
Whenever the Am79C978A controller is the current bus
master and a data parity error occurs, SINT (CSR5, bit
11) will be set to 1. When SINT is set, INTA is asserted
if the enable bit SINTE (CSR5, bit 10) is set to 1. This
mechanism can be used to inform the driver of the sys-
tem error. The host can read the PCI Status register to
determine the exact cause of the interrupt. The setting
of SINT due to a data parity error is not dependent on
the setting of PERREN (PCI Command register, bit 6).
By default, a data parity error does not affect the
state of the MAC engine. TheAm79C978A control-
ler treats the data in all bus master transfers that
have a parity error as if nothing has happened. All
network activity continues.
Advanced Parity Error Handling
For all DMA cycles, the Am79C978A controller provides
a second, more advanced level of parity error handling.
This mode is enabled by setting APERREN (BCR20, bit
10) to 1. When APERREN is set to 1, the BPE bits (RMD1
and TMD1, bit 23) are used to indicate parity error in data
transfers to the receive and transmit buffers. Note that
since the advanced parity error handling uses an addi-
tional bit in the descriptor, SWSTYLE (BCR20, bits 7-0)
must be set to 2 or 3 to program the Am79C978A con-
troller to use 32-bit software structures. TheAm79C978A
controller will react in the following way when a data parity
error occurs:
Initialization block read: STOP (CSR0, bit 2) is set
to 1 and causes a STOP_RESET of the device.
Descriptor ring read: Any on-going network activity
is terminated in an orderly sequence and then STOP
(CSR0, bit 2) is set to 1 to cause a STOP_RESET
of the device.
Descriptor ring write: Any on-going network activity
is terminated in an orderly sequence and then STOP
(CSR0, bit 2) is set to 1 to cause a STOP_RESET
of the device.
Transmit buffer read: BPE (TMD1, bit 23) is set in
the current transmit descriptor. Any on-going net-
work transmission is terminated in an orderly se-
quence.
Receive buffer write: BPE (RMD1, bit 23) is set in
the last receive descriptor associated with the frame.
Terminating on-going network transmission in an
orderly sequence means that if less than 512
bits have been transmitted onto the network, the
transmission will be terminated immediately,
generating a runt packet.
If 512 bits or more have been transmitted, the mes-
sage will have the current FCS inverted and ap-
pended at the next byte boundary to guarantee an
FCS error is detected at the receiving station.
APERREN does not affect the reporting of address
parity errors or data parity errors that occur when the
Am79C978A controller is the target of the transfer.
Initialization Block DMA Transfers
During execution of the Am79C978A controller bus
master initialization procedure, the microcode will re-
peatedly request DMA transfers from the BIU. During
each of these initialization block DMA transfers, the
BIU will perform two data transfer cycles reading one
DWord per transfer and then it will relinquish the bus.
When SSIZE32 (BCR20, bit 8) is set to 1 (i.e., the ini-
tialization block is organized as 32-bit software struc-
tures), there are seven DWords to transfer during the
bus master initialization procedure, so four bus mas-
tership periods are needed in order to complete the
initialization sequence. Note that the last DWord
transfer of the last bus mastership period of the initial-
ization sequence accesses an unneeded location.
Data from this transfer is discarded internally. When
SSIZE32 is cleared to 0 (i.e., the initialization block is
organized as 16-bit software structures), then three
bus mastership periods are needed to complete the
initialization sequence.
The Am79C978A device supports two transfer modes
for reading the initialization block: non-burst and burst
mode, with burst mode being the preferred mode
when the Am79C978A controller is used in a PCI bus
application. See Figure 25 and Figure 26.
When BREADE is cleared to 0 (BCR18, bit 6), all
initialization block read transfers will be executed in
non-burst mode. There is a new address phase for
every data phase. FRAME will be dropped between
the two transfers. The two phases within a bus mas-
tership period will have addresses of ascending
contiguous order.
When BREADE is set to 1 (BCR18, bit 6), all initializa-
tion block read transfers will be executed in burst
mode. AD[1:0] will be 0 during the address phase indi-
cating a linear burst order.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C978 | Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C981 | Integrated Multiport Repeater Plus⑩ (IMR+⑩) |
| AM79C981JC | Integrated Multiport Repeater Plus⑩ (IMR+⑩) |
| AM79C982 | basic Integrated Multiport Repeater (bIMR) |
| AM79C982-4JC | basic Integrated Multiport Repeater (bIMR) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C978KC/W | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C978VC/W | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C979BKC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C98 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Twisted-Pair Ethernet Transceiver (TPEX) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。