參數(shù)資料
型號(hào)： AM79C978AVCW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： Single-Chip 1/10 Mbps PCI Home Networking Controller
中文描述： 5 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝： TQFP-144
文件頁(yè)數(shù)： 157/256頁(yè)
文件大?。?/td> 3505K
代理商： AM79C978AVCW
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Am79C978A
157
Table 38.
PHY Select Programming
These bits are read accessible al-
ways, these bits can only be writ-
ten from the EEPROM unless a
write-enable bit, BCR2[13], is set.
PHYSEL [1:0] is cleared by
H_RESET and is not affected by
S_RESET or STOP.
2-0
LINBC
Reserved locations. These bits
are read accessible always; write
accessible only when either the
STOP or the SPND bit is set. Af-
ter H_RESET, the value in these
bits will be 001b. The setting of
these bits have no effect on any
Am79C978A controller
’
s func-
tion. LINBC is not affected by
S_RESET or STOP.
BCR19: EEPROM Control and Status
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15
PVALID
EEPROM Valid status bit. This bit
is read accessible only. PVALID
is read only; write operations
have no effect. A value of 1 in this
bit indicates that a PREAD opera-
tion has occurred, and that (1)
there is an EEPROM connected
to the Am79C978A controller in-
terface pins and (2) the contents
read from the EEPROM have
passed the checksum verification
operation.
A value of 0 in this bit indicates a
failure in reading the EEPROM.
The checksum for the entire 82
bytes of EEPROM is incorrect or
no EEPROM is connected to the
interface pins.
PVALID is set to 0 during
H_RESET and is unaffected by
S_RESET or the STOP bit. How-
ever, following the H_RESET op-
eration, an automatic read of the
EEPROM will be performed. Just
as it is true for the normal PREAD
command, at the end of this auto-
matic read operation the PVALID
bit may be set to 1. Therefore,
H_RESET will set the PVALID bit
to 0 at first, but the automatic EE-
PROM read operation may later
set PVALID to a 1.
If PVALID becomes 0 following an
EEPROM read operation (either
automatically
generated
H_RESET, or requested through
PREAD), then all EEPROM-pro-
grammable BCR locations will be
reset to their H_RESET values.
The content of the Address
PROM locations, however, will not
be cleared.
after
If no EEPROM is present at the
EESK, EEDI, and EEDO pins,
then all attempted PREAD
commands will terminate early
and PVALID will
not
be set.
This applies to the automatic
read of the EEPROM after
H_RESET, as well as to host-
initiated PREAD commands.
14
PREAD
EEPROM Read command bit.
When this bit is set to a 1 by the
host, the PVALID bit (BCR19, bit
15) will immediately be reset to a
0, and then the Am79C978A con-
troller will perform a read opera-
tion of 82 bytes from the
EEPROM through the interface.
The EEPROM data that is
fetched during the read will be
stored in the appropriate internal
registers on board the controller.
Upon completion of the EEPROM
read operation, the Am79C978A
controller will assert the PVALID
bit. EEPROM contents will be in-
directly accessible to the host
through read accesses to the Ad-
dress PROM (offsets 0h through
Fh) and through read accesses to
other EEPROM programmable
registers. Note that read access-
es from these locations will not
actually access the EEPROM it-
self, but instead will access the
Am79C978A internal copy of the
EEPROM
contents.
Write
PHYSEL [1:0]
00
01
10
11
Mode
Expansion ROM/Flash
EADI/Internal MII Snoop
Reserved
Reserved
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