參數(shù)資料
型號(hào)： AK4671
廠商： Asahi Kasei Microsystems Co.,Ltd
元件分類： Codec
英文描述： Stereo CODEC with MIC/RCV/HP-AMP
中文描述： 立體聲編解碼器麥克風(fēng)/垃圾車/惠普腺苷
文件頁(yè)數(shù)： 51/164頁(yè)
文件大小： 1792K
代理商： AK4671
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[AK4671]
MS0666-E-00
2007/10
- 51 -
■
System Reset
When power-up, the AK4671 should be reset by bringing the PDN pin = “L”. This ensures that all internal registers reset
to their initial values.
The ADC enters an initialization cycle that starts when the PMADL or PMADR bit is changed from “0” to “1” at PMDAL
and PMDAR bits are “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the
ADC digital data outputs of both channels are forced to a 2’s complement, “0”. The ADC output reflects the analog input
signal after the initialization cycle is complete. When PMDAL or PMDAR is “1”, the ADC does not require an
initialization cycle.
■
Audio Interface Format
Four types of data formats are available and can be selected by setting the DIF1-0 bits (
Table 16
). In all modes, the serial
data is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. LRCK
and BICK are output from the AK4671 in master mode, but must be input to the AK4671 in slave mode.
Mode
DIF1 bit
DIF0 bit
SDTO (ADC)
0
0
0
DSP Mode
1
0
1
MSB justified
LSB justified
2
1
0
MSB justified
MSB justified
3
1
1
I
2
S compatible
I
2
S compatible
Table 16. Audio Interface Format
In modes 1, 2 and 3, the SDTO is clocked out on the falling edge (“
↓
”) of BICK and the SDTI is latched on the rising edge
(“
↑
”).
In Modes 0 (DSP mode), the audio I/F timing is changed by BCKP and MSBS bits (
Table 17
).
DIF1
DIF0
MSBS
BCKP
Audio Interface Format
MSB of SDTO is output by the rising edge (“
↑
”) of the
first BICK after the rising edge (“
↑
”) of LRCK.
MSB of SDTI is latched by the falling edge (“
↓
”) of the
BICK just after the output timing of SDTO’s MSB.
MSB of SDTO is output by the falling edge (“
↓
”) of the
first BICK after the rising edge (“
↑
”) of LRCK.
MSB of SDTI is latched by the rising edge (“
↑
”) of the
BICK just after the output timing of SDTO’s MSB.
MSB of SDTO is output by next rising edge (“
↑
”) of the
falling edge (“
↓
”) of the first BICK after the rising edge
(“
↑
”) of LRCK.
MSB of SDTI is latched by the falling edge (“
↓
”) of the
BICK just after the output timing of SDTO’s MSB.
MSB of SDTO is output by next falling edge (“
↓
”) of the
rising edge (“
↑
”) of the first BICK after the rising edge
(“
↑
”) of LRCK.
MSB of SDTI is latched by the rising edge (“
↑
”) of the
BICK just after the output timing of SDTO’s MSB.
Table 17. Audio Interface Format in Mode 0
If 16-bit data that ADC outputs is converted to 8-bit data by removing LSB 8-bit, “
1” at 16bit data is converted to “
1”
at 8-bit data. And when the DAC playbacks this 8-bit data, “
1” at 8-bit data will be converted to “
256” at 16-bit data
and this is a large offset. This offset can be removed by adding the offset of “128” to 16-bit data before converting to 8-bit
data.
SDTI (DAC)
DSP Mode
BICK
≥
32fs
≥
32fs
≥
32fs
≥
32fs
Figure
Table 17
Figure 49
Figure 50
Figure 51
(default)
Figure
0
0
Figure 45
(default)
0
1
Figure 46
1
0
Figure 47
0
0
1
1
Figure 48
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AK4671_10 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/RCV/HP-AMP
AK4671EG 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/RCV/HP-AMP
AK4673 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/HP-AMP and Touch Screen Controller
AK4673EG 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/HP-AMP and Touch Screen Controller
AK4675 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/RCV/HP/SPK-AMP
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