
[AK4671] 
MS0666-E-00 
2007/10 
- 45 - 
When PLL reference clock input is LRCK or BICK pin, the sampling frequency is selected by FS3-2 bits (
Table 6
). 
Mode 
FS3 bit 
FS2 bit 
FS1 bit 
0 
0 
0 
x 
1 
0 
1 
x
2 
1 
x
x
Others 
Others 
FS0 bit 
x
x
x
Sampling Frequency Range 
8kHz 
≤
 fs 
≤
 12kHz 
12kHz < fs 
≤
 24kHz 
24kHz < fs 
≤
 48kHz 
N/A 
(x: Don’t care, N/A: Not available) 
(default)
Table 6. Setting of Sampling Frequency at PMPLL bit = “1” (Reference Clock = LRCK or BICK pin) 
■
 PLL Unlock State 
1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”) 
In this mode, LRCK and BICK pins go to “L” and irregular frequency clock is output from the MCKO pin at MCKO bit 
is “1” before the PLL goes to lock state after PMPLL bit = “0” 
 “1”. If MCKO bit is “0”, the MCKO pin changes to “L” 
(
Table 7
). 
After the PLL is locked, a first period of LRCK and BICK may be invalid clock, but these clocks return to normal state 
after a period of 1/fs. 
When sampling frequency is changed, BICK and LRCK pins do not output irregular frequency clocks but go to “L” by 
setting PMPLL bit to “0”. 
MCKO pin 
PLL State 
MCKO bit = “0”
After that PMPLL bit “0” 
 “1” 
“L” Output 
PLL Unlock (except above case) 
“L” Output 
PLL Lock 
“L” Output 
Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”) 
2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”) 
In this mode, an invalid clock is output from the MCKO pin before the PLL goes to lock state after PMPLL bit = “0” 
“1”. After that, the clock selected by 
Table 9
 is output from the MCKO pin when PLL is locked. ADC and DAC output 
invalid data when the PLL is unlocked. For DAC, the output signal should be muted by writing “0” to DACL and DACH 
bits. 
MCKO bit  = “1” 
Invalid 
Invalid 
See 
Table 9
BICK pin 
LRCK pin 
“L” Output 
Invalid 
See 
Table 10
“L” Output 
Invalid 
1fs Output 
MCKO pin 
PLL State 
MCKO bit = “0”
“L” Output 
“L” Output 
“L” Output 
MCKO bit = “1” 
Invalid 
Invalid 
Output 
After that PMPLL bit “0” 
 “1” 
PLL Unlock 
PLL Lock 
Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = “0”, M/S bit = “0”)