參數(shù)資料
型號(hào)： AK4671
廠商： Asahi Kasei Microsystems Co.,Ltd
元件分類： Codec
英文描述： Stereo CODEC with MIC/RCV/HP-AMP
中文描述： 立體聲編解碼器麥克風(fēng)/垃圾車/惠普腺苷
文件頁(yè)數(shù)： 153/164頁(yè)
文件大小： 1792K
代理商： AK4671
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[AK4671]
MS0666-E-00
2007/10
- 153 -
■
Headphone-Amp Output
FS3-0 bits
(Addr:01H, D7-4)
OVL/R7-0 bits
(Addr:1AH&1BH, D7-0)
PML/RO2 bits
(Addr:10H, D1-0)
MUTEN bit
(Addr:10H, D2)
LOUT2 pin
ROUT2 pin
1111
0000
18H
28H
Normal Output
(1)
EQ bit
(Addr:18H, D3)
0
1
0
(3)
(4)
(11)
PMDAL/R bits
(Addr:00H, D7-6)
(5)
(10)
(6)
(8)
(7)
(9)
PML/RO2S bits
(Addr:10H, D6-5)
DACHL/R bits
(Addr:0B&0CH, D0)
(12)
HPG3-0 bits
(Addr:08H, D7-4)
1011
1010
(2)
E x am ple :
P LL M aster M od e
A ud io I/F F orm at: M S B jus tified (A D C & D A C )
S am plin g Frequ enc y: 44.1 kH z
O V O LC b it = “1” (d efault)
D igital V olum e L evel:
8 dB
H P V olu m e L e vel:
3d B
5 b an d E Q : E n able
(1) A ddr:01H , D ata:F 4H
(4) A ddr:1A H & 1B H , D ata 28H
(5) A ddr:00H , D ata C 1H
P layback
(3) A ddr:18H , D ata 0A H
(8) A ddr:10H , D ata 63H
(9) A ddr:10H , D ata 00H
(6) A ddr:10H , D ata 63H
(7) A ddr:10H , D ata 67H
(10) A ddr:00H , D ata 01H
(11) A ddr:18H , D ata 02H
(2) A ddr:08H , D ata A 5H
A ddr:0B H & 0C H , D ata 01H
(12) A ddr:0B H & 0C H , D ata 00H
Figure 115. Headphone-Amp Output Sequence
(Headphone Playback: SDTI
→
Audio I/F
→
EQ
→
DATT
→
DACL/R
→
LOUT2/ROUT2)
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1)
Set up a sampling frequency (FS3-0 bits). When the AK4671 is PLL mode, DAC and Headphone-Amp should
be powered-up in consideration of PLL lock time after a sampling frequency is changed.
(2)
Set up the path of “SDTI
DAC
HP-Amp”: DACHL = DACHR bits = “0”
→
“1”
Set up analog volume for HP-Amp (Addr: 08H, HPG3-0 bits)
(3)
Enable 5-band Equalizer: EQ bit = “0”
“1” (Boost amount is selected by Addr = 50H-52H.)
(4)
Set up the output digital volume (Addr: 1AH and 1BH)
When OVOLC bit is “1” (default), OVL7-0 bits set the volume of both channels. After DAC is powered-up,
the digital volume changes from default value (0dB) to the register setting value by the soft transition.
(5)
Power up DAC: PMDAL = PMDAR bits = “0”
→
“1”
(6)
Power up Headphone-Amp and MIX-Amp: PMLO2 = PMRO2 = PMLO2S = PMRO2S bits = “0”
→
“1”
Output voltages of Headphone-Amp are still VSS1.
(7)
Rise up the common voltage of Headphone-Amp: MUTEN bit = “0”
→
“1”
The rise time depends on AVDD and the capacitor value connected with the MUTET pin. When AVDD=3.3V
and the capacitor value is 1.0
μ
F, the time constant is
τ
r = 250ms(max.).
(8)
Fall down the common voltage of Headphone-Amp: MUTEN bit = “1”
→
“0”
The fall time depends on AVDD and the capacitor value connected with the MUTET pin. When AVDD=3.3V
and the capacitor value is 1.0
μ
F, the time constant is
τ
f = 250ms(max.).
If the power supply is powered-off or Headphone-Amp is powered-down before the common voltage goes to
VSS2, the pop noise occurs. It takes twice of
τ
f that the common voltage goes to VSS2.
(9)
Power down Headphone-Amp and MIX-Amp: PMLO2 = PMRO2 = PMLO2S = PMRO2S bits = “1”
→
“0”
(10)
Power down DAC: PMDAL = PMDAR bits = “1”
→
“0”
(11)
Disable 5-band Equalizer: EQ bit = “1”
“0”
(12)
Disable the path of “DAC
→
Headphone-Amp”: DACHL = DACHR bits = “1”
→
“0”
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