
[AK4671] 
MS0666-E-00 
2007/10 
- 19 - 
Parameter 
PLL Slave Mode (PLL Reference Clock = LRCK pin)
LRCK Input Timing 
Frequency 
DSP Mode: Pulse Width High 
Except DSP Mode: Duty Cycle 
BICK Input Timing 
Period 
Pulse Width Low 
Pulse Width High 
PLL Slave Mode (PLL Reference Clock = BICK pin)
LRCK Input Timing 
Frequency 
DSP Mode: Pulse Width High 
Except DSP Mode: Duty Cycle 
BICK Input Timing 
Period 
PLL3-0 bits = “0010” 
PLL3-0 bits = “0011” 
Pulse Width Low 
Pulse Width High 
External Slave Mode
MCKI Input Timing 
Frequency 
256fs 
384fs 
512fs 
768fs 
1024fs 
Pulse Width Low 
Pulse Width High 
LRCK Input Timing 
Frequency 
256fs/384fs 
512fs/768fs 
1024fs 
DSP Mode: Pulse Width High 
Except DSP Mode: Duty Cycle 
BICK Input Timing 
Period 
Pulse Width Low 
Pulse Width High 
External Master Mode
MCKI Input Timing 
Frequency 
256fs 
384fs 
512fs 
768fs 
1024fs 
Pulse Width Low 
Pulse Width High 
LRCK Output Timing 
Frequency 
DSP Mode: Pulse Width High 
Except DSP Mode: Duty Cycle 
BICK Output Timing 
Period 
BCKO bit = “0” 
BCKO bit = “1” 
Duty Cycle 
Symbol
min 
typ 
max 
Units
fs 
8 
- 
- 
- 
48 
kHz 
ns 
% 
tLRCKH
Duty 
tBCK
60 
45 
1/fs 
 tBCK
55 
tBCK 
tBCKL 
tBCKH
1/(64fs) 
130 
130 
- 
- 
- 
1/(32fs) 
- 
- 
ns 
ns 
ns 
fs 
8 
- 
- 
- 
48 
kHz 
ns 
% 
tLRCKH
Duty 
tBCK
60 
45 
1/fs 
 tBCK
55 
tBCK 
tBCK 
tBCKL 
tBCKH
- 
- 
1/(32fs) 
1/(64fs) 
- 
- 
- 
- 
- 
- 
ns 
ns 
ns 
ns 
0.4 x tBCK
0.4 x tBCK
fCLK 
fCLK 
fCLK 
fCLK 
fCLK 
tCLKL 
tCLKH 
2.048 
3.072 
4.096 
6.144 
8.192 
0.4/fCLK 
0.4/fCLK 
- 
- 
- 
- 
- 
- 
- 
12.288 
18.432 
13.312 
19.968 
13.312 
- 
- 
MHz 
MHz 
MHz 
MHz 
MHz 
ns 
ns 
fs 
fs 
fs 
8 
8 
8 
- 
- 
- 
- 
- 
48 
26 
13 
kHz 
kHz 
kHz 
ns 
% 
tLRCKH
Duty 
tBCK
60 
45 
1/fs 
 tBCK
55 
tBCK 
tBCKL 
tBCKH
312.5 
130 
130 
- 
- 
- 
- 
- 
- 
ns 
ns 
ns 
fCLK 
fCLK 
fCLK 
fCLK 
fCLK 
tCLKL 
tCLKH 
2.048 
3.072 
4.096 
6.144 
8.192 
0.4/fCLK 
0.4/fCLK 
- 
- 
- 
- 
- 
- 
- 
12.288 
18.432 
13.312 
19.968 
13.312 
- 
- 
MHz 
MHz 
MHz 
MHz 
MHz 
ns 
ns 
fs 
8 
- 
- 
- 
48 
- 
- 
kHz 
ns 
% 
tLRCKH
Duty 
tBCK 
50 
tBCK 
tBCK 
dBCK 
- 
- 
- 
1/(32fs) 
1/(64fs) 
50 
- 
- 
- 
ns 
ns 
%