
[AK4671] 
MS0666-E-00 
2007/10 
- 5 - 
No. Pin Name 
J8 
SDTIA 
G8 BICKA 
H9 SYNCA 
G9 SDTOA 
F8 
TVDD2 
F9 
VSS2 
E8 
PVDD 
I/O 
I 
I/O 
I/O 
O 
- 
- 
- 
Function 
Serial Data Input A Pin 
Serial Data Clock A Pin 
Sync Signal A Pin 
Serial Data Output A Pin 
Digital I/O Power Supply 2 Pin, 1.6 
~
 3.6V 
Ground 2 Pin 
PLLBT Power Supply Pin, 2.2  
~
 3.6V 
Output Pin for Loop Filter of PLLBT Circuit 
This pin should be connected to VSS2 pin with one resistor and capacitor in series.
Output Pin for Loop Filter of PLL Circuit 
This pin should be connected to VSS1 pin with one resistor and capacitor in series.
Common Voltage Output Pin, 0.5 x AVDD 
Bias voltage of ADC inputs and DAC outputs. 
Mute Time Constant Control Pin 
Connected to VSS1 pin with a capacitor for mute time constant. 
Rch Headphone-Amp Output Pin 
Lch Headphone-Amp Output Pin 
Test Pin 
This pin should be open. 
Analog Power Supply Pin, 2.2  
~
 3.6V 
Ground 1 Pin 
Rch Stereo Line Output 1 Pin (RCV bit = “0”: Stereo Line Output) 
Receiver-Amp Negative Output Pin (RCV bit = “1”: Receiver Output) 
Lch Stereo Line Output 1 Pin (RCV bit = “0”: Stereo Line Output) 
Receiver-Amp Positive Output Pin (RCV bit = “1”: Receiver Output) 
Rch Stereo Line Output 3 Pin (LODIF bit = “0”: Single-ended Stereo Output) 
Negative Line Output Pin (LODIF bit = “1”: Full-differential Mono Output) 
Lch Stereo Line Output 3 Pin (LODIF bit = “0”: Single-ended Stereo Output) 
Positive Line Output Pin (LODIF bit = “1”: Full-differential Mono Output) 
Rch Analog Input 4 Pin (MDIF4 bit = “0”: Single-ended Input) 
Negative Line Input 4 Pin (MDIF4 bit = “1”: Full-differential Input) 
Lch Analog Input 4 Pin (MDIF4 bit = “0”: Single-ended Input) 
Positive Line Input 4 Pin (MDIF4 bit = “1”: Full-differential Input) 
Rch Analog Input 3 Pin (MDIF3 bit = “0”: Single-ended Input) 
Negative Line Input 3 Pin (MDIF3 bit = “1”: Full-differential Input) 
Lch Analog Input 3 Pin (MDIF3 bit = “0”: Single-ended Input) 
Positive Line Input 3 Pin (MDIF3 bit = “1”: Full-differential Input) 
Rch Analog Input 2 Pin (MDIF2 bit = “0”: Single-ended Input) 
Negative Line Input 2 Pin (MDIF2 bit = “1”: Full-differential Input) 
Lch Analog Input 2 Pin (MDIF2 bit = “0”: Single-ended Input) 
Positive Line Input 2 Pin (MDIF2 bit = “1”: Full-differential Input) 
Rch Analog Input 1 Pin (MDIF1 bit = “0”: Single-ended Input) 
Negative Line Input 1 Pin (MDIF1 bit = “1”: Full-differential Input) 
Lch Analog Input 1 Pin (MDIF1 bit = “0”: Single-ended Input) 
Positive Line Input 1 Pin (MDIF1 bit = “1”: Full-differential Input) 
No Connect Pin 
No internal bonding. This pin should be open or connected to the ground. 
Note 1. All input pins except analog input pins (MDT, LIN1/IN1+, RIN1/IN1
, LIN2/IN2+, RIN2/IN2
, LIN3/IN3+, 
RIN3/IN3
, LIN4/IN4+, RIN4/IN4
, SAIN1, SAIN2, SAIN3) should not be left floating. 
I/O pins except SDA pin (LRCK, BICK, SYNCA, BICKA, SYNCB, BICKB) should be processed appropriately. 
Please refer the “
Master Mode/Slave Mode
” (P.45) and “
PCM I/F Master Mode/Slave Mode
” (P.105). SDA pin 
should be pulled-up by a resistor externally and be connected to (DVDD+0.3)V or less voltage. 
E9 
VCOCBT 
O 
D8 VCOC 
O 
D9 VCOM 
O 
C8 
MUTET 
O 
C9 
B9 
ROUT2 
LOUT2 
O 
O 
A9 TEST 
- 
A8 AVDD 
B8 
VSS1 
ROUT1 
B7 
RCN 
LOUT1 
A7 
RCP 
ROUT3 
A6 
LON 
LOUT3 
B6 
LOP 
RIN4 
A5 
IN4
LIN4 
B5 
IN4+ 
RIN3 
B4 
IN3
LIN3 
A4 
IN3+ 
RIN2 
B3 
IN2
LIN2 
A3 
IN2+ 
RIN1 
B2 
IN1
LIN1 
A2 
IN1+ 
- 
- 
O 
O 
O 
O 
O 
O 
O 
O 
I 
I 
I 
I 
I 
I 
I 
I 
I 
I 
I 
I 
I 
I 
I 
I 
C3 
NC 
-