
[AK4671] 
MS0666-E-00 
2007/10 
- 50 - 
■
 EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”) 
The AK4671 becomes EXT Master Mode by setting PMPLL bit = “0” and M/S bit = “1”. Master clock is input from the 
MCKI pin, the internal PLL circuit is not operated. The clock required to operate is MCKI (256fs, 384fs, 512fs, 768fs or 
1024fs). The input frequency of MCKI is selected by FS2-0 bits (
Table 13
). 
Mode 
FS3 bit 
FS2 bit 
FS1 bit 
FS0 bit 
MCKI Input 
Frequency 
256fs 
1024fs 
384fs 
768fs 
512fs 
256fs 
N/A 
(x: Don’t care, N/A: Not available) 
Sampling Frequency 
Range 
8kHz 
~
 48kHz 
8kHz 
~
 13kHz 
8kHz 
~
 48kHz 
8kHz 
~
 26kHz 
8kHz 
~
 26kHz 
8kHz 
~
 48kHz 
N/A 
0 
1 
4 
5 
6 
7 
x 
x
x 
x 
x
x
0 
0 
1 
1 
1 
1 
0 
0 
0 
0 
1 
1 
0 
1 
0 
1 
0 
1 
(default)
Others 
Others
Table 13. MCKI Frequency at EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”)
The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. 
The out-of-band noise can be reduced by using higher frequency of the master clock. The S/N of the DAC output through 
LOUT/ROUT pins at fs=8kHz is shown in 
Table 14
. 
MCKI 
S/N 
(fs=8kHz, 20kHzLPF + A-weighted)
83dB 
93dB 
93dB 
256fs, 384fs 
512fs, 768fs 
1024fs 
Table 14. Relationship between MCKI and S/N of LOUT1/ROUT1 pins
MCKI should always be present whenever the ADC or DAC is in operation (PMADL bit = “1”, PMADR bit = “1”, 
PMDAL bit = “1” or PMDAR bit = “1”). If MCKI is not provided, the AK4671 may draw excess current and it is not 
possible to operate properly because utilizes dynamic refreshed logic internally. If MCKI is not present, the ADC and 
DAC should be in the power-down mode (PMADL=PMADR=PMDAL=PMDAR bits = “0”). 
AK4671 
DSP or 
μ
P
MCKI 
BICK 
LRCK 
SDTO 
SDTI 
BCLK 
LRCK 
SDTI 
SDTO 
MCKO 
1fs
32fs or 64fs
MCLK 
256fs, 384fs, 512fs, 
 768fs or 1024fs 
Figure 44. EXT Master Mode 
BCKO bit 
BICK Output 
Frequency 
32fs 
64fs 
0 
1 
(default) 
Table 15. BICK Output Frequency at Master Mode