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參數(shù)資料
| 型號： | AK4371VN |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | DAC with built-in PLL & HP-AMP |
| 中文描述： | DAC，帶有內(nèi)置的鎖相環(huán) |
| 文件頁數(shù)： | 60/62頁 |
| 文件大?。?/td> | 842K |
| 代理商： | AK4371VN |
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[AK4371]
MS0596-E-00
2007/04
- 60 -
110k
100k
AK4371
LIN1 pin
AVDD
LIN1HL bit
HP-Amp
Note: If the path is OFF and the signal is input to the input pin, the input pin should be biased to a voltage equivalent to
VCOM voltage (= 0.475 x AVDD) externally.
Figure 46. External Bias Circuit Example for Line Input Pin
1. Grounding and Power Supply Decoupling
The AK4371 requires careful attention to power supply and grounding arrangements. AVDD, PVDD and HVDD are
usually supplied from the analog power supply in the system and DVDD is supplied from AVDD via a 10
Ω
resistor.
Alternatively if AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or
more. When the AK4371 is powered-down, DVDD should be powered-down at the same time or later than AVDD. When
AVDD and HVDD are supplied separately, AVDD should be powered-up at the same time or earlier than HVDD. When
the AK4371 is powered-down, AVDD should be powered-down at the same time or later than HVDD. The power up
sequence of PVDD is not critical. VSS1, VSS2 and VSS3 must be connected to the analog ground plane. System analog
ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit
board. Decoupling capacitors should be as close to the AK4371 as possible, with the small value ceramic capacitors being
the nearest.
2. Voltage Reference
When PMVREF bit = “0”, the input voltage to AVDD sets the analog output range. Usually a 0.1
μ
F ceramic capacitor is
connected between AVDD and VSS1. When PMVREF bit = “1”, VREF is the reference voltage of analog signal (typ.
0.855 x AVDD). The capacitor around 0.22
μ
F attached between VREF and VSS1 eliminates the effects of high
frequency noise. VCOM is a signal ground of this chip (0.475 x AVDD). The electrolytic capacitor around 2.2
μ
F attached
between VCOM anVSS1 eliminates the effects of high frequency noise, too. No load current may be drawn from VREF
and VCOM pin. All signals, especially clock, should be kept away from AVDD, VREF and VCOM in order to avoid
unwanted coupling into the AK4371.
3. Analog Outputs
The analog outputs are single-ended outputs, and 0.48 x AVDD Vpp(typ)@
3dBFS (PMVREF bit = “0”) for
headphone-amp and 0.61xAVDD Vpp(typ) @0dBFS (PMVREF bit = “0”) for LOUT/ROUT/MOUT centered on the
VCOM voltage. The input data format is 2’s compliment. The output voltage is a positive full scale for
7FFFFFH(@24bit) and negative full scale for 800000H(@24bit). The ideal output is VCOM voltage for
000000H(@24bit).
DC offsets on the analog outputs is eliminated by AC coupling since the analog outputs have a DC offset equal to VCOM
plus a few mV.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4372 | 制造商:AKM 制造商全稱:AKM 功能描述:DAC with built-in PLL & HP-AMP |
| AK4372ECB | 制造商:AKM 制造商全稱:AKM 功能描述:DAC with built-in PLL & HP-AMP |
| AK4372VCB | 制造商:AKM 制造商全稱:AKM 功能描述:DAC with built-in PLL & HP-AMP |
| AK4373 | 制造商:AKM 制造商全稱:AKM 功能描述:Low Power Stereo DAC with HP/SPK-Amp |
| AK4373EN | 制造商:AKM 制造商全稱:AKM 功能描述:Low Power Stereo DAC with HP/SPK-Amp |
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