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參數(shù)資料
| 型號(hào)： | AK4371VN |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | DAC with built-in PLL & HP-AMP |
| 中文描述： | DAC，帶有內(nèi)置的鎖相環(huán) |
| 文件頁數(shù)： | 38/62頁 |
| 文件大?。?/td> | 842K |
| 代理商： | AK4371VN |
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[AK4371]
MS0596-E-00
2007/04
- 38 -
■
Power-Up/Down Sequence (EXT mode)
1) DAC
→
HP-Amp
Power Supply
(1)
>150ns
PDN pin
PMVCM bit
Clock Input
(3)
SDTI pin
PMDAC bit
DAC Internal
State
PD
Normal Operation
HPL/R pin
PMHPL,
PMHPR bits
(6)
ATTL7-0
ATTR7-0 bits
00H(MUTE)
FFH(0dB)
(8) GD (9) 1061/fs
PD
Normal Operation
00H(MUTE)
FFH(0dB)
(8)
(9)
(6)
(7)
(8) (9)
Don’t care
Don’t care
(7)
(8) (9)
00H(MUTE)
Don’t care
(10)
Don’t care
(2) >0s
PD
(5) >2ms
MUTEN bit
DALHL,
DARHR bits
(4) >0s
(4) >0s
(5) >2ms
Figure 29. Power-up/down sequence of DAC and HP-amp (Don’t care: except Hi-Z)
(1)
When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or
more. When AVDD and HVDD are supplied separately, AVDD should be powered-up at the same time or earlier
than HVDD. PDN pin should be set to “H” at least 150ns after power is supplied.
(2)
PMVCM and PMDAC bits should be changed to “1” after PDN pin goes “H”.
(3)
External clocks (MCKI, BICK, LRCK) are needed to operate the DAC. When the PMDAC bit = “0”, these clocks
can be stopped. The headphone-amp can operate without these clocks.
(4)
DALHL and DARHR bits should be changed to “1” after PMVCM and PMDAC bit is changed to “1”.
(5)
PMHPL, PMHPR and MUTEN bits should be changed to “1” at least 2ms (in case external capacitance at VCOM pin
is 2.2
μ
F) after the DALHL and DARHR bits are changed to “1”
(6)
Rise time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The rise time up to
VCOM/2 is t
r
= 70k x C(typ). When C=1
μ
F, t
r
= 70ms(typ).
(7)
Fall time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The fall time down to
VCOM/2 is t
f
= 60k x C(typ). When C=1
μ
F, t
f
= 60ms(typ).
PMHPL and PMHPR bits should be changed to “0” after HPL and HPR pins go to VSS1. After that, the DALHL and
DARHR bits should be changed to “0”.
(8)
Analog output corresponding to the digital input has a group delay (GD) of 22/fs(=499μs@fs=44.1kHz).
(9)
The ATS bit sets transition time of digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz).
(10)
The power supply should be switched off after the headphone-amp is powered down (HPL/R pins become “L”).
When AVDD and DVDD are supplied separately, DVDD should be powered-down at the same time or later than
than HVDD.
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