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參數(shù)資料
| 型號(hào)： | AK4371VN |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | DAC with built-in PLL & HP-AMP |
| 中文描述： | DAC，帶有內(nèi)置的鎖相環(huán) |
| 文件頁數(shù)： | 24/62頁 |
| 文件大?。?/td> | 842K |
| 代理商： | AK4371VN |
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[AK4371]
MS0596-E-00
2007/04
- 24 -
■
EXT Mode (PMPLL bit = “0”: Default)
The AK4371 can be placed in external clock mode (EXT mode) by setting the PMPLL bit to “0”. In EXT mode, the
master clock can directly input to the DAC via the MCKI pin without going through the PLL. In this case, the sampling
frequency and MCKI frequency can be selected by FS3-0 bits (Table 11). In EXT mode, PLL4-0 bits are ignored. MCKO
output is enabled by controlling the MCKO bit. MCKO output frequency can be controlled by PS1-0 bits. If the sampling
frequency is changed during normal operation of the DAC (PMDAC bit = “1”), the change should occur after the input is
muted by SMUTE bit = “1”, or the input is set to “0” data.
LRCK and BICK are output from the AK4371 in master mode(Figure 15). The clock input to the MCKI pin should
always be present whenever the DAC is in normal operation (PMDAC bit = “1”). If these clocks are not provided, the
AK4371 may draw excessive current and will not operate properly because it utilizes these clocks for internal dynamic
refresh of registers. If the external clocks are not present, the DAC should be placed in power-down mode (PMDAC bit =
“0”).
AK4371
DSP or
μ
P
MCKI
BICK
LRCK
SDATA
BCLK
LRCK
SDTO
MCKO
1fs
32fs, 64fs
MCLK
256fs, 384fs, 512fs,
768fs or 1024fs
Figure 15. EXT Master Mode
The external clocks required to operate the AK4371 in slave mode are MCKI, LRCK and BICK(Figure 16). The master
clock (MCKI) should be synchronized with the sampling clock (LRCK). The phase between these clocks does not matter.
All external clocks (MCKI, BICK and LRCK) should always be present whenever the DAC is in normal operation mode
(PMDAC bit = “1”). If these clocks are not provided, the AK4371 may draw excessive current and will not operate
properly, because it utilizes these clocks for internal dynamic refresh of registers. If the external clocks are not present, the
DAC should be placed in power-down mode (PMDAC bit = “0”).
AK4371
DSP or
μ
P
MCKI
BICK
LRCK
SDATA
BCLK
LRCK
SDTO
MCKO
1fs
32fs
~
64fs
MCLK
256fs, 384fs, 512fs,
768fs or 1024fs
Figure 16. EXT Slave Mode
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4372 | 制造商:AKM 制造商全稱:AKM 功能描述:DAC with built-in PLL & HP-AMP |
| AK4372ECB | 制造商:AKM 制造商全稱:AKM 功能描述:DAC with built-in PLL & HP-AMP |
| AK4372VCB | 制造商:AKM 制造商全稱:AKM 功能描述:DAC with built-in PLL & HP-AMP |
| AK4373 | 制造商:AKM 制造商全稱:AKM 功能描述:Low Power Stereo DAC with HP/SPK-Amp |
| AK4373EN | 制造商:AKM 制造商全稱:AKM 功能描述:Low Power Stereo DAC with HP/SPK-Amp |
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