參數(shù)資料
型號(hào): AK4371VN
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: DAC with built-in PLL & HP-AMP
中文描述: DAC,帶有內(nèi)置的鎖相環(huán)
文件頁數(shù): 26/62頁
文件大?。?/td> 842K
代理商: AK4371VN
[AK4371]
MS0596-E-00
2007/04
- 26 -
Serial Data Interface
The AK4371 interfaces with external systems via the SDATA, BICK and LRCK pins. Five data formats are available,
selected by setting the DIF2, DIF1 and DIF0 bits (Table 16). Mode 0 is compatible with existing 16-bit DACs and digital
filters. Mode 1 is a 20-bit version of Mode 0. Mode 4 is a 24-bit version of Mode 0. Mode 2 is similar to AKM ADCs and
many DSP serial ports. Mode 3 is compatible with the I
2
S serial data protocol. In Modes 2 and 3 with BICK
48fs, the
following formats are also valid: 16-bit data followed by eight zeros (17th to 24th bits) and 20-bit data followed by four
zeros (21st to 24th bits). In all modes, the serial data is MSB first and 2’s complement format.
When master mode and BICK=32fs(BF bit = “0”), the AK4371 cannot be set to Mode 1 Mode 2 or Mode 4.
Mode
DIF2
DIF1
DIF0
Format
0
0
0
0
0: 16bit, LSB justified
1
0
0
1
1: 20bit, LSB justified
2
0
1
0
2: 24bit, MSB justified
3
0
1
1
3: I
2
S Compatible
4
1
0
0
4: 24bit, LSB justified
Table 16. Audio Data Format
LRCK
BICK
Figure
Figure 17
Figure 18
Figure 19
32fs
BICK
64fs
40fs
BICK
64fs
48fs
BICK
64fs
BICK=32fs or 48fs
BICK
64fs Figure 20
48fs
BICK
64fs
(default)
Figure 18
SDATA
Mode 0
BICK
(32fs)
SDATA
Mode 0
15
14
6
5
4
BICK
3
2
1
0
15
14
15
14
0
15
14
0
Don’t care
Don’t care
15:MSB, 0:LSB
15
14
6
5
4
3
2
1
0
Lch Data
Rch Data
Figure 17. Mode 0 Timing (LRP = BCKP bits = “0”)
SDATA
Mode 1
LRCK
BICK
19
0
19
0
Don’t care
Don’t care
19:MSB, 0:LSB
SDATA
Mode 4
23:MSB, 0:LSB
20
19
0
20 19
0
Don’t care
Don’t care
22
21
22
21
Lch Data
Rch Data
23
23
Figure 18. Mode 1, 4 Timing (LRP = BCKP bits = “0”)
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