參數(shù)資料
型號(hào)： AK4371VN
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： DAC with built-in PLL & HP-AMP
中文描述： DAC，帶有內(nèi)置的鎖相環(huán)
文件頁數(shù)： 43/62頁
文件大小： 842K
代理商： AK4371VN
[AK4371]
MS0596-E-00
2007/04
- 43 -
6) LIN1/RIN1/LIN2/RIN2/LIN3/RIN3
→
MOUT
Power Supply
PDN pin
PMVCM bit
MOUT pin
(6)
MMUTE,
ATTM3-0 bits
10H(MUTE)
0FH(0dB)
(Hi-Z)
(Hi-Z)
(6)
(6)
LIN1/RIN1/
LIN2/RIN2/
LIN3/RIN3 pins
(4)
(Hi-Z)
(Hi-Z)
PMMO bit
Don’t care
(1) >150ns
(2) >0s
LIN1M, RIN1M,
LIN2M, RIN2M,
LIN3M, RIN3M bits
(3) >0s
(5) >2ms
(5) >2ms
Figure 34. Power-up/down sequence of LIN1/RIN1/LIN2/RIN2/LIN3/RIN3 and MOUT
(1)
When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or
more. When AVDD and HVDD are supplied separately, AVDD should be powered-up at the same time or earlier
than HVDD. PDN pin should be set to “H” at least 150ns after power is supplied. MCKI, BICK and LRCK can be
stopped when DAC is not used.
(2)
PMVCM bit should be changed to “1” after PDN pin goes “H”.
(3)
LIN1M, LIN2M, LIN3M, RIN1M, RIN2M and RIN3M bits should be changed to “1” after PMVCM bit is changed
to “1”.
(4)
When LIN1M, LIN2M, LIN3M, RIN1M, RIN2M or RIN3M bit is changed to “1”, LIN1, RIN1, LIN2, RIN2, LIN3
or RIN3 pin is biased to 0.475 x AVDD.
(5)
PMMO bit should be changed to “1” at least 2ms (in case external capacitance at VCOM pin is 2.2
μ
F) after LIN1M,
LIN2M, LIN3M, RIN1M, RIN2M or RIN3M bits are changed to “1”.
(6)
When the PMMO bit is changed, pop noise is output from MOUT pins.
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