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參數(shù)資料
| 型號(hào)： | AK4371VN |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | DAC with built-in PLL & HP-AMP |
| 中文描述： | DAC，帶有內(nèi)置的鎖相環(huán) |
| 文件頁數(shù)： | 20/62頁 |
| 文件大?。?/td> | 842K |
| 代理商： | AK4371VN |
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[AK4371]
MS0596-E-00
2007/04
- 20 -
When PLL reference clock input is LRCK or BICK pin, the sampling frequency is selected by FS3-0 bits. (Table 6)
Mode
FS3 bit
FS2 bit
FS1 bit
0
1
0
0
1
1
0
0
2
1
0
1
3
1
0
1
4
1
1
0
Others
Others
Table 6. Setting of Sampling Frequency (PLL reference clock input is LRCK or BICK pin)
FS0 bit
0
1
0
1
0
Sampling Frequency Range
32kHz < fs
≤
48kHz
24kHz < fs
≤
32kHz
16kHz < fs
≤
24kHz
12kHz < fs
≤
16kHz
8kHz
≤
fs
≤
12kHz
N/A
(default)
■
PLL Unlock State
1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
In master mode (M/S bits = “1”), LRCK and BICK pins output “L” before the PLL is locked by setting PMPLL =
PMDAC bits = “0”
“1”. At that time, MCKO pin outputs an abnormal frequency clock at MCKO bit = “1”. When
MCKO bit = “0”, MCKO pin outputs “L”. After the PLL is locked, LRCK and BICK start to output the clocks (Table 7).
Master Mode (M/S bit = “1”)
Power Up
(PMDAC bit= PMPLL bit= “1”)
(PMDAC bit= PMPLL bit= “0”)
MCKI pin
Refer to Table 4.
Input or
fixed to “L” or “H” externally
MCKO pin MCKO bit = “0”: “L”
MCKO bit = “1”: Output
BICK pin
BF bit = “1”: 64fs output
BF bit = “0”: 32fs output
LRCK pin
Output
“L”
Table 7. Clock Operation in Master mode (PLL mode)
2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
In slave mode (M/S bits = “0”), an invalid clock is output from MCKO pin when MCKO bit = “1”, before the PLL is
locked by setting PMPLL = PMDAC bits = “0”
“1”. When MCKO bit = “0”, MCKO pin outputs “L”. After the PLL is
locked, MCKO starts to output the clocks (Table 9).
Slave Mode (M/S bit = “0”)
Power Up
(PMDAC bit= PMPLL bit= “1”)
(PMDAC bit= PMPLL bit= “0”)
MCKI pin
Refer to Table 4.
Input or
fixed to “L” or “H” externally
MCKO pin MCKO bit = “0”: “L”
MCKO bit = “1”: Output
BICK pin
Input
Fixed to “L” or “H” externally
Power Down
PLL Unlock
Refer to Table 4.
“L”
MCKO bit = “0”: “L”
MCKO bit = “1”: Unsettling
“L”
“L”
“L”
Power Down
PLL Unlock
Refer to Table 4.
“L”
MCKO bit = “0”: “L”
MCKO bit = “1”: Unsettling
Input or
Fixed
to
“L”
externally
Input or
Fixed
to
“L”
externally
or
“H”
LRCK pin
Input
Fixed to “L” or “H” externally
or
“H”
Table 8. Clock Operation in Slave mode (PLL mode)
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