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參數(shù)資料
| 型號(hào)： | AK4371VN |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | DAC with built-in PLL & HP-AMP |
| 中文描述： | DAC，帶有內(nèi)置的鎖相環(huán) |
| 文件頁數(shù)： | 35/62頁 |
| 文件大?。?/td> | 842K |
| 代理商： | AK4371VN |
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[AK4371]
MS0596-E-00
2007/04
- 35 -
■
Stereo Line Output (LOUT, ROUT pins)
The common voltage is 0.475 x AVDD. The load resistance is 10k
Ω
(min). When the PMLO bit is “1”, the stereo line
output is powered-up. DALL, LIN1L, RIN1L, LIN2L, RIN2L, LIN3L and RIN3L bits control each path switch of LOUT.
DARR, LIN1R, RIN1R, LIN2R, RIN2R, LIN3R and RIN3R bits control each path switch of ROUT. When L1M = L2M
= L3M bits = “0”, LOG bit = “0” (R
1L
= R
2L
= R
3L
= R
DL
= 100k) and ATTS3-0 bits is “0FH”(0dB), the mixing gain is
0dB(typ) for all paths. When the LOG bit = “1”(R
DL
= 50k), the DAC path gain is +6dB. When L1M = L2M = L3M bits =
“1”, LIN1/RIN1, LIN2/RIN2 and LIN3/RIN3 signals are output from LOUT/ROUT pins as (L+R)/2 respectively (R
1L
=
R
2L
= R
3L
= 200k).
If the path is OFF and the signal is input to the input pin, the input pin should be biased to a voltage equivalent to VCOM
voltage (= 0.475 x AVDD) externally. Figure 46 shows the external bias circuit example.
R
1L
+
LOUT pin
RIN3 pin
R
L
R
DL
R
3L
RIN3L bit
DALL bit
+
100k(typ)
R
L
RIN2 pin
LIN3 pin
R
3L
R
2L
RIN2L bit
LIN3L bit
LIN2 pin
R
2L
LIN2L bit
DAC Lch
RIN1 pin
R
1L
RIN1L bit
LIN1 pin
LIN1L bit
+
ROUT pin
RIN3 pin
R
L
R
DL
R
3L
RIN3R bit
DARR bit
+
100k(typ)
R
L
RIN2 pin
LIN3 pin
R
3L
R
2L
RIN2R bit
LIN3R bit
LIN2 pin
R
2L
LIN2R bit
DAC Rch
RIN1 pin
R
1L
RIN1R bit
LIN1 pin
R
1L
LIN1R bit
Figure 26. Summation circuit for stereo line output
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相關(guān)代理商/技術(shù)參數(shù) |
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| AK4372 | 制造商:AKM 制造商全稱:AKM 功能描述:DAC with built-in PLL & HP-AMP |
| AK4372ECB | 制造商:AKM 制造商全稱:AKM 功能描述:DAC with built-in PLL & HP-AMP |
| AK4372VCB | 制造商:AKM 制造商全稱:AKM 功能描述:DAC with built-in PLL & HP-AMP |
| AK4373 | 制造商:AKM 制造商全稱:AKM 功能描述:Low Power Stereo DAC with HP/SPK-Amp |
| AK4373EN | 制造商:AKM 制造商全稱:AKM 功能描述:Low Power Stereo DAC with HP/SPK-Amp |
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