參數(shù)資料
型號(hào)： ADUC7039BCP6Z-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 87/92頁(yè)
文件大小： 0K
描述： IC MCU ARM7 BATT SENSER 32LFCSP
標(biāo)準(zhǔn)包裝： 2,500
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 20.48MHz
連通性： LIN，SPI
外圍設(shè)備： POR，溫度傳感器，WDT
輸入/輸出數(shù)： 6
程序存儲(chǔ)器容量： 64KB（32K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 1K x 32
電壓 - 電源 (Vcc/Vdd)： 3.5 V ~ 18 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 115°C
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
包裝： 帶卷 (TR)
ADuC7039
Data Sheet
Rev. D | Page 88 of 92
PART IDENTIFICATION
For traceability, part identification is available at power-up.
Information such as manufacturing lot ID, silicon mask
revision, and kernel revision are available in the internal
ARM register at power-up (R4 to R6), as described in Table 65
For full traceability, R4, R5, R6 and part numbers need to
be recorded. The assembly lot ID stored in R6 is part of the
branding on the package as shown Table 63.
For example, for an assembly lot ID of 2528206.1, R6
contains 0x002693CE. The part number is contained in the
MMR FEEADR at power-up.
Table 63. Branding Example ADuC7039BCP6Z
Line
LFCSP
Line 1
ADuC7039
Line 2
BCP6Z
Line 3
B60 #date code
Line 4
2528206.1
Table 64. Branding Example ADuC7039WBCPZ
Line
LFCSP
Line 1
ADuC7039
Line 2
WBCPZ
Line 3
D60 #date code
Line 4
2528206.1
Line5
MALAYSIA
Table 65. R4 Bit Designations at Power-Up
Bit
Description
31 to 27
Wafer number. The five bits read from this location give the wafer number (1 to 24) from the wafer fabrication lot ID
(from which this device originated). When used in conjunction with R4[26:0], it provides individual wafer traceability.
26 to 22
Wafer lot fabrication plant. The five bits read from this location reflect the manufacturing plant associated with this
wafer lot. When it is used in conjunction with R4[21:0], it provides wafer lot traceability.
21 to 16
Wafer lot fabrication ID. The six bits read from this location form part of the wafer lot fabrication ID, and when used in
conjunction with R4[26:22] and R4[15:0], the bits provide wafer lot traceability.
15 to 0
Wafer lot fabrication ID. These 16 LSBs hold a 16-bit number to be interpreted as the wafer fabrication lot ID number.
When used in conjunction with the value in R5, that is, the manufacturing lot ID, this number is a unique identifier for
the part.
Table 66. R5 Bit Designations at Power-Up
Bit
Description
31 to 28
Silicon mask revision ID. The 4 bits read from this nibble reflect the silicon mask ID number. Specifically, the hex value in
this nibble should be decoded as the lower hex nibble in the hex numbers reflecting the ASCII characters in the range of
A to O. For example,
Bits[19:16] = 0001 = 0x1; therefore, this value should be interpreted as 41 which is ASCII Character A corresponding to
Silicon Mask Revision A.
Bits[19:16] = 1011 = 0xB; therefore the number is interpreted as 4B which is ASCII Character K corresponding to Silicon
Mask Revision K.
The allowable range for this value is 1 to 15 which is interpreted as 41 to 4F or ASCII Character A to Character O.
27 to 20
Kernel revision ID. This byte contains the hex number, which should be interpreted as an ASCII character indicating the
revision of the kernel firmware embedded in the on-chip Flash/EE memory. For example, reading 0x41 from this byte
should be interpreted as A indicating a Revision A kernel is on-chip.
19 to 16
Reserved. For prerelease samples, these bits refer to the kernel minor revision number of the device.
15 to 0
Part ID. These 16 LSBs hold a 16-bit number that are interpreted as the part ID number. When used in conjunction with
the value in R4 (that is, the manufacturing lot ID) this number is a unique identifier for the part.
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