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| 型號(hào)： | ADUC7039BCP6Z-RL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 67/92頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU ARM7 BATT SENSER 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 20.48MHz |
| 連通性： | LIN，SPI |
| 外圍設(shè)備： | POR，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 6 |
| 程序存儲(chǔ)器容量： | 64KB（32K x 16） |
| 程序存儲(chǔ)器類(lèi)型： | 閃存 |
| RAM 容量： | 1K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 3.5 V ~ 18 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 115°C |
| 封裝/外殼： | 32-VFQFN 裸露焊盤(pán)，CSP |
| 包裝： | 帶卷 (TR) |
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Data Sheet
ADuC7039
Rev. D | Page 7 of 92
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
VDD = 7.0 V … 18 V
tBIT = 96 s
D4 = tBUS_REC(MAX)/(2 × tBIT)
tRX_PDR1, 20
Propagation delay of receiver
6
s
tRX_SYM1, 20
Symmetry of receiver propagation delay rising edge,
with respect to falling edge (tRX_SYM = tRF_PDR tRX_PDF)
2
+2
s
PACKAGE THERMAL SPECIFICATIONS
Thermal Impedance (θJA)21
32-lead CSP, stacked die
32
°C/W
POWER REQUIREMENTS1
Power Supply Voltages
VDD (Battery Supply)
3.5
18
V
REG_DVDD, REG_AVDD22
2.45
2.6
2.75
V
Power Consumption
ADC off (20.48 MHz)
10
20
mA
ADC off (10.24 MHz)
7.5
16
mA
ADC low power mode, measured over an ambient
temperature range of TA = 10°C to +40°C, continuous ADC
conversion
750
1000
A
Precision oscillator turned off, ADC off
Average current, measured with wake-up and watchdog
timers clocked from low power oscillator (40°C to +85°C)
95
300
A
Average current, measured with wake-up and watchdog
timers clocked from low power oscillator over an ambient
temperature range of 10°C to +40°C
95
175
A
IDD (Current ADC)
1.7
mA
IDD (Voltage/Temperature ADC)
0.5
mA
IDD (Precision Oscillator)
400
A
1
Not guaranteed by production test but by design and/or characterization data at production release.
2
Valid for current ADC gain setting of PGA up to 64.
3
These numbers include temperature drift.
4
The offset error drift is included in the offset error. This typical specification is an indicator of the offset error due to temperature drift. This typical value is the mean of
the temperature drift characterization data distribution.
5
Includes internal reference temperature drift.
6
User system calibration removes this error at a given temperature and at a given gain on the current channel.
7
The gain drift is included in the total gain error. This typical specification is an indicator of the gain error due to temperature drift. This typical value is the mean of the
temperature drift characterization data distribution.
8
Voltage channel specifications include resistive attenuator input stage.
9
RMS noise is referred to voltage attenuator input; for example, at fADC = 1 kHz, typical rms noise at the ADC input is 7.5 V, scaled by the attenuator (24) yields these
input referred noise figures.
10
Valid after an initial self calibration.
11
It is possible to extend the ADC input range by up to 10% by modifying the factory set value of the gain calibration register or using system calibration. This approach
can also be used to reduce the ADC input range (LSB size).
12
In ADC low power mode, the input range is fixed at ±2.34375 mV.
13
Valid for a differential input less than 10 mV.
14
The absolute value of the voltage of VTEMP and GND_SW must be 100mV minimum, for accurate operation of the T-ADC.
15
Measured using box method.
16
The long-term stability specification is noncumulative. The drift in subsequent 1000 hour periods is significantly lower than in the first 1000 hour period.
17
Die temperature.
18
Endurance is qualified to 10,000 cycles, as per JEDEC Std. 22 Method A117 and measured at 40°C, +25°C, and +125°C. Typical endurance at 25°C is 170,000 cycles.
19
Retention lifetime equivalent at junction temperature (TJ) = 85°C, as per JEDEC Std. 22 Method A117. Retention lifetime derates with junction temperature.
20
These numbers are not production tested but are supported by LIN compliance testing.
21
Thermal impedance can be used to calculate the thermal gradient from ambient to die temperature.
22
Internal regulated supply available at REG_DVDD (ISOURCE = 5 mA) and REG_AVDD (ISOURCE =1 mA).
23
Typical additional supply current consumed during Flash/EE memory program and erase cycles is 7 mA and 5 mA, respectively.
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