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| 型號： | ADUC7039BCP6Z-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU ARM7 BATT SENSER 32LFCSP |
| 標準包裝： | 2,500 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 20.48MHz |
| 連通性： | LIN，SPI |
| 外圍設(shè)備： | POR，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 6 |
| 程序存儲器容量： | 64KB（32K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 3.5 V ~ 18 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 115°C |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 包裝： | 帶卷 (TR) |
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Data Sheet
ADuC7039
Rev. D | Page 15 of 92
MEMORY ORGANIZATION
The ARM7, a von Neumann architecture, MCU core sees mem-
the ADuC7039 maps this into four distinct user areas, namely: a
memory area that can be remapped, an SRAM area, a Flash/EE
area, and a memory mapped register (MMR) area.
Figure 5. ADuC7039 Memory Map, 64 kB Flash Option
The first 64 kB of this memory space is used as an area into
which the on-chip Flash/EE or SRAM can be remapped.
The ADuC7039 features a second 4 kB area at the top of
the memory map used to locate the MMRs, through which
all on-chip peripherals are configured and monitored.
The ADuC7039 features an SRAM size of 4 kB.
The ADuC7039 features 64 kB of on-chip Flash/EE
memory. However, 62 kB of on-chip Flash/EE memory are
available to the user. In addition, 2 kB are reserved for the
on-chip kernel.
Any access, either reading or writing, to an area not defined in
the memory map results in a data abort exception.
Memory Format
The ADuC7039 memory organization is configured in little
endian format: the least significant byte is located in the lowest
byte address, and the most significant byte in the highest byte
address.
Figure 6. Little Endian Format
SRAM
The ADuC7039 features 4 kB of SRAM, organized as 1024 × 32
bits, that is, 1024 words, which is located at 0x40000.
The RAM space can be used as data memory and also as a
volatile program space.
ARM code can run directly from SRAM at full clock speed
given that the SRAM array is configured as a 32-bit wide
memory array. SRAM is read/writeable in 8-, 16-, and 32-bit
segments.
Remap
The ARM exception vectors are all situated at the bottom
of the memory array, from Address 0x00000000 to Address
0x00000020.
By default, after a reset, the Flash/EE memory is logically mapped
to Address 0x00000000. It is possible to logically remap the
SRAM to Address 0x00000000. This is accomplished by setting
Bit 0 of the SYSMAP MMR located at 0xFFFF0220. To revert
Flash/EE to 0x00000000, Bit 0 of SYSMAP is cleared.
It is sometimes desirable to remap RAM to 0x00000000 to
execute code from SRAM while erasing a page of Flash/EE
memory.
Remap Operation
When a reset occurs on the ADuC7039, execution starts auto-
matically in the factory programmed internal configuration
code. This so-called kernel is hidden and cannot be accessed
by user code. If the ADuC7039 is in normal mode, it executes
the power-on configuration routine of the kernel and then
jumps to the reset vector, Address 0x00000000, to execute the
user’s reset exception routine. Because the Flash/EE is mirrored
at the bottom of the memory array at reset, the reset routine
must always be written in Flash/EE.
0x0040FFF
0x00040000
0xFFFF0FFF
0xFFFF0000
MMRs
0x0008FFFF
0x00080000
FLASH/EE
SRAM
0x0000F7FF
0x00000000
REMAPPABLE MEMORY SPACE
(FLASH/EE OR SRAM)
RESERVED
08463-
005
BIT 31
BYTE 2
A
6
2
.
BYTE 3
B
7
3
.
BYTE 1
9
5
1
.
BYTE 0
8
4
0
.
BIT 0
32 BITS
0xFFFFFFFF
0x00000004
0x00000000
08463-
007
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