參數(shù)資料
型號： ADUC7039BCP6Z-RL
廠商： Analog Devices Inc
文件頁數(shù)： 86/92頁
文件大?。?/td> 0K
描述： IC MCU ARM7 BATT SENSER 32LFCSP
標準包裝： 2,500
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 20.48MHz
連通性： LIN，SPI
外圍設備： POR，溫度傳感器，WDT
輸入/輸出數(shù)： 6
程序存儲器容量： 64KB（32K x 16）
程序存儲器類型： 閃存
RAM 容量： 1K x 32
電壓 - 電源 (Vcc/Vdd)： 3.5 V ~ 18 V
數(shù)據(jù)轉換器： A/D 2x16b
振蕩器型： 內部
工作溫度： -40°C ~ 115°C
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
包裝： 帶卷 (TR)
Data Sheet
ADuC7039
Rev. D | Page 87 of 92
Table 62. LINSTA MMR Bit Designations
Bits
Description
15 to 11
Reserved.
10
LIN wake-up interrupt.
This bit is set if LIN woke up the ADuC7039. The wake-up functionality (LINWU MMR) is only used when POWCON[3] = 0.
This bit is cleared automatically by a read of the LINSTA MMR.
9
Break time maximum.
This bit is 0 if the first break symbol after enabling the LIN interface has ended before maximum count reached.
This bit is 1 if the first break symbol after enabling the LIN interface has ended after maximum count reached.
This bit is cleared automatically by hardware when reading LINSTA MMR.
This bit is only valid on the first break symbol after enabling the LIN peripheral via LINCON[11].
8
PID parity error.
This bit is set automatically by hardware if the current byte in the LINDAT register does not correctly match the parity scheme for
a PID as described in the LIN 2.1 specifications.
This bit is cleared by hardware if the current byte in the LINDAT register correctly matches the parity scheme for a PID.
It is left to the user to determine when a PID is actually in the data register. The parity check is done whether a PID or data byte is
in the LINDAT MMR.
7
Checksum match.
This bit is only valid when LINSTA[0] = 1.
This bit is set automatically if the value in LINCS does not match the received data in LINDAT.
This bit is cleared on a read of the LINSTA MMR or when LINDAT and LINCS match while LINSTA[0] = 1.
6
Frame error.
This bit is 0 if there is no frame error. It is cleared automatically by a read of LINSTA.
This bit is 1 if a frame error has occurred during reception of a data byte, that is, a valid stop was not detected.
5
Negative edge maximum error interrupt (maskable).
This bit is 0 if the number of negative edges allowed in a frame is not surpassed.
This bit is 1 if the number of negative edges is 57 or more.
This bit is cleared automatically by hardware when reading LINSTA MMR.
4
LIN collision detect interrupt (maskable).
This bit is set automatically by hardware if the device has stopped transmission due to a collision on the bus. This bit is not set
if the collision detect and transmit complete interrupt is enabled (LINCON[6] = 0) and the transmit complete interrupt bit is set
(LINSTA[2] = 1).
This bit is cleared automatically by hardware when reading LINSTA MMR.
3
Break receive interrupt (maskable).
This bit is 0 if no valid break symbol has been received.
This bit is 1 if a low time of 11 nominal bits is detected on the LIN bus. This bit is cleared automatically on reading the LINSTA MMR.
2
Transmit complete interrupt (maskable).
This bit is 0 if data is still in the LINDAT register.
This bit is 1 when all data is transmitted. It remains set to 1 until the LIN receives a break symbol. It is cleared automatically in
receive mode.
1
Transmit ready interrupt (maskable).
This bit is 0 if the previous data written in the LINDAT MMR is still in the LINDAT and has not being shifted to the transmit
register. Writing data to the LINDAT MMR while the transmit ready bit is 0 overwrites the previous byte to be transmitted.
This bit is 1 if the previous data written in the LINDAT MMR is now in the transmit register.
0
Receive ready interrupt.
This bit is 0 if there is no new data to read in the LINDAT MMR.
This bit is 1 if there is new data to read in the LINDAT MMR. Reading the LINDAT MMR clears this bit.
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