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| 型號： | ADUC7039BCP6Z-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 29/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU ARM7 BATT SENSER 32LFCSP |
| 標準包裝： | 2,500 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 20.48MHz |
| 連通性： | LIN，SPI |
| 外圍設備： | POR，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 6 |
| 程序存儲器容量： | 64KB（32K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 3.5 V ~ 18 V |
| 數(shù)據(jù)轉換器： | A/D 2x16b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 115°C |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 包裝： | 帶卷 (TR) |
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Data Sheet
ADuC7039
Rev. D | Page 35 of 92
ADC Interrupt Mask Register
Name:
ADCMSKI
Address:
0xFFFF0504
Default Value:
0x00
Access:
Read/write
Function:
This register allows the ADC interrupt sources to be individually enabled. The bit positions in this register are
the same as the lower eight bits in the ADCSTA MMR. If a bit is set by user code to a 1, the respective interrupt
is enabled. By default, all bits are 0, meaning all ADC interrupt sources are disabled. Note that ADCMSKI[2:0]
should not be set if ADCMSKI[5] is set.
ADC Mode Register
Name:
ADCMDE
Address:
0xFFFF0508
Default Value:
0x00
Access:
Read/write
Function:
The ADC mode MMR is an 8-bit register that configures the mode of operation of the ADC subsystem.
Table 28. ADCMDE MMR Bit Designations
Bit
Description
7 to 6
Not used. These bits are reserved for future functionality and should be written as 0 by user code.
5
ADC enable continuous interrupt.
This bit is set to 1 to enable ADCSTA[5].
This bit is set to 0 by default.
4
Reserved.
3
ADC power mode configuration.
0 = ADC normal mode. If enabled, the ADC operates with normal current consumption yielding optimum electrical performance.
1 = ADC low power mode. If enabled, the ADC operates with reduced current consumption. In this mode, the gain is fixed to 512.
2 to 0
ADC operation mode configuration.
0, 0, 0 = ADC power-down mode. All ADC circuits are powered down.
0, 0, 1 = ADC continuous conversion mode. In this mode, any enabled ADC continuously converts.
0, 1, 0 = ADC single conversion mode. In this mode, any enabled ADC performs a single conversion. The ADC enters idle mode when the
single shot conversion is complete. A single conversion takes two to three ADC clock cycles depending on the chop mode.
0, 1, 1 = ADC idle mode. In this mode, the ADC is fully powered on but is held in reset.
1, 1, 0 = ADC system zero-scale calibration. In this mode, a zero-scale calibration is performed on enabled ADC channels against
an external zero-scale voltage applied to the ADC input pins. The calibration is carried out at the user programmed ADC settings;
therefore, as with a normal, single ADC conversion, it takes the full ADC filter settling time before a fully settled calibration result is
ready. The results (offset coefficients) are available in the ADCxDAT MMR when ADCSTA[15] is set. User software should copy the
result of the conversion to the ADCxOF MMR.
1, 1, 1 = ADC system full-scale calibration. In this mode, a full-scale calibration is performed on enabled ADC channels against an
external full-scale voltage applied to the ADC input pins. The results (gain coefficients) are available in the ADCxDAT MMR when
ADCSTA[15] is set. User software should copy the result of the conversion to the ADCxGN MMR.
Other = reserved.
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