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| 型號： | ADUC7039BCP6Z-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 32/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU ARM7 BATT SENSER 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 20.48MHz |
| 連通性： | LIN，SPI |
| 外圍設(shè)備： | POR，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 6 |
| 程序存儲器容量： | 64KB（32K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 3.5 V ~ 18 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 115°C |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 包裝： | 帶卷 (TR) |
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ADuC7039
Data Sheet
Rev. D | Page 38 of 92
ADC Filter Register
Name:
ADCFLT
Address:
0xFFFF0518
Default Value:
0x0007
Access:
Read/write
Function:
The ADC filter MMR is a 16-bit register that controls the speed and resolution of the on-chip ADCs.
Note:
If ADCFLT is modified, the current and voltage/temperature ADCs are reset. It is recommended that all bits of this
MMR are written in a single write operation.
Table 31. ADCFLT MMR Bit Designations
Bit
Description
15
Chop enable.
This bit is set by the user to enable system chopping of all active ADCs. When this bit is set, the ADC has very low offset
errors and drift, but the ADC output rate is reduced by a factor of three if AF = 0 (see sinc3 decimation factor, Bits[6:0] in
this table). If AF > 0, then the ADC output update rate is the same with chop on or off. When chop is enabled, the
settling time is two output periods.
14
Running average.
This bit is set by the user to enable a running-average-by-two function reducing ADC noise. This function is automatically
enabled when chopping is active. It is an optional feature when chopping is inactive, and if enabled (when chopping
is inactive) does not reduce the ADC output rate but does increase the settling time by one conversion period.
This bit is cleared by the user to disable the running average function.
13 to 8
Averaging factor (AF).
The values written to these bits are used to implement a programmable first-order sinc3 postfilter. The averaging factor
can further reduce ADC noise at the expense of the output rate as described in Bits[6:0] sinc3 decimation factor in this
table.
7
Sinc3 modify.
This bit is set by the user to modify the standard sinc3 frequency response to increase the filter stop-band rejection by
approximately 5 dB. This is achieved by inserting a second notch (NOTCH2) at
fNOTCH2 = 1.333 × fNOTCH
where fNOTCH is the location of the first notch in the response.
6 to 0
Sinc3 decimation factor (SF)1.
The value (SF) written in these bits controls the oversampling (decimation factor) of the sinc3 filter. The output rate
from the sinc3 filter is given by
fADC = (512,000/([SF + 1] × 64)) Hz
when the chop bit (Bit 15, chop enable) = 0 and the averaging factor (AF) = 0. This is valid for all SF values ≤ 125.
For SF = 126, fADC is forced to 60 Hz.
For SF = 127, fADC is forced to 50 Hz.
For information on calculating the fADC for SF (other than 126 and 127) and AF values, refer to Table 32.
1
Due to limitations on the digital filter internal data path, there are some limitations on the combinations of the sinc3 decimation factor (SF) and averaging factor (AF)
that can be used to generate a required ADC output rate. This restriction limits the minimum ADC update to 10 Hz.
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