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| 型號： | ADUC7039BCP6Z-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/92頁 |
| 文件大小： | 0K |
| 描述： | IC MCU ARM7 BATT SENSER 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 20.48MHz |
| 連通性： | LIN，SPI |
| 外圍設(shè)備： | POR，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 6 |
| 程序存儲器容量： | 64KB（32K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 3.5 V ~ 18 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 115°C |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 包裝： | 帶卷 (TR) |
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ADuC7039
Data Sheet
Rev. D | Page 16 of 92
The remap command must be executed from the absolute
Flash/EE address, and not from the mirrored, remapped
segment of memory, because this may be replaced by SRAM. If
a remap operation is executed while operating code from
the mirrored location, prefetch/data aborts can occur, or the
user can observe abnormal program operation.
Any kind of reset logically remaps the Flash/EE memory to
the bottom of the memory array.
SYSMAP Register
Name:
SYSMAP
Address:
0xFFFF0220
Default Value: Updated by the kernel
Access:
Read/write
Function:
This 8-bit register allows user code to remap
either RAM or Flash/EE space into the bottom
of the ARM memory space starting at Address
0x00000000.
Table 7. SYSMAP MMR Bit Designations
Bit
Description
7 to 1
Reserved. These bits are reserved and should be written
as 0 by user code.
0
Remap bit.
This bit is set by the user to remap the SRAM to
0x00000000.
This bit is cleared automatically after reset to remap the
Flash/EE memory to 0x00000000.
RESET
There are four kinds of reset: external reset, power-on-reset,
watchdog reset, and software reset. The RSTSTA register
indicates the source of the last reset and can also be written
by user code to initiate a software reset event. The bits in this
register can be cleared to 0 by writing to the RSTCLR MMR at
0xFFFF0234. The bit designations in RSTCLR mirror those of
RSTSTA. These registers can be used during a reset exception
service routine to identify the source of the reset. The implica-
tions of all four kinds of reset event are tabulated in Table 9.
RSTSTA Register
Name:
RSTSTA
Address:
0xFFFF0230
Default Value: N/A
Access:
Read/write
Function:
This 8-bit register indicates the source of the
last reset event and can also be written by user
code to initiate a software reset.
RSTCLR Register
Name:
RSTCLR
Address:
0xFFFF0234
Access:
Write only
Function: This 8-bit write-only register clears the
corresponding bit in RSTSTA.
Table 8. RSTSTA/RSTCLR MMR Bit Designations
Bit
Description
7 to 4
Not used. These bits are not used and always read as 0.
3
External reset.
This bit is set by hardware when an external reset occurs.
This bit is cleared by setting the corresponding bit in RSTCLR.
2
Software reset.
This bit is set by user code to generate a software reset.
This bit is cleared by setting the corresponding bit in RSTCLR.1
1
Watchdog timeout.
This bit is set by hardware when a watchdog timeout occurs.
This bit is cleared by setting the corresponding bit in RSTCLR.
0
Power-on reset.
This bit is set by hardware when a power-on-reset occurs.
This bit is cleared by setting the corresponding bit in RSTCLR.
1
If the software reset bit in RSTSTA is set, any write to RSTCLR that does not
clear this bit generates a software reset.
Table 9. Device Reset Implications
Impact
RESET
Reset External
Pins to Default
State
Kernel
Executed
Reset All External
MMRs (Excluding
RSTSTA)
Reset All HV
Indirect
Registers
Peripherals
Reset
Watchdog
Timer Reset
RAM
Valid1
RSTSTA (Status
After Reset Event)
POR
Yes
Yes/No2
RSTSTA[0] = 1
Watchdog
Yes
No
Yes
RSTSTA[1] = 1
Software
Yes
No
Yes
RSTSTA[2] = 1
External Pin
Yes
No
Yes
RSTSTA[3] = 1
1
RAM is not valid in the case of a reset following LIN download.
2
The impact on RAM is dependent on the HVSTA[2] contents if LVF is enabled. When LVF is enabled using HVCFG[4], RAM has not been corrupted by the POR reset
mechanism if the LVF Status Bit HVSTA[2] is 1. See the Low Voltage Flag (LVF) section for more information.
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