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| 型號： | AD9995KCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD SIGNAL PROCESSOR 56-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | CCD 信號處理器，12 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 電流 - 電源： | 30mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 56-LFCSP-VQ（8x8） |
| 包裝： | 托盤 |
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AD9995
–17–
Table V.Vertical Pattern Group Registers
Register
Length
Range
Description
VPOL
1b
High/Low
Starting Polarity of Each V1–V6 Output
VTOG1
12b
0–4096 Pixel Location
First Toggle Position within Line for Each V1–V6 Output
VTOG2
12b
0–4096 Pixel Location
Second Toggle Position within Line for Each V1–V6 Output
VTOG3
12b
0–4096 Pixel Location
Third Toggle Position within Line for Each V1–V6 Output
VTOG4
12b
0–4096 Pixel Location
Fourth Toggle Position, only Available in V-Pattern Groups 8 and 9
VPATLEN
12b
0–4096 Pixels
Total Length of Each V-Pattern Group
FREEZE1
12b
0–4096 Pixel Location
Holds the V1–V6 Outputs at Their Current Levels (Static DC)
RESUME1
12b
0–4096 Pixel Location
Resumes Operation of the V1–V6 Outputs to Finish Their Pattern
FREEZE2
12b
0–4096 Pixel Location
Holds the V1–V6 Outputs at Their Current Levels (Static DC)
RESUME2
12b
0–4096 Pixel Location
Resumes Operation of the V1–V6 Outputs to Finish Their Pattern
HD
V1
PROGRAMMABLE SETTINGS FOR EACH V-PATTERN:
1. START POLARITY
2. FIRST TOGGLE POSITION
3. SECOND TOGGLE POSITION (3RD TOGGLE POSITION ALSO AVAILABLE, 4TH TOGGLE POSITION AVAILABLE FOR V-PATTERN GROUPS 8 AND 9)
4. TOTAL PATTERN LENGTH FOR ALL V1-V6 OUTPUTS
START POSITION OF V-PATTERN GROUP IS PROGRAMMABLE IN V-SEQUENCE REGISTERS
4
1
2
3
V2
1
2
3
V6
1
2
3
Figure 16. Vertical Pattern Group Programmability
Vertical Pattern Groups (VPAT)
The vertical pattern groups define the individual pulse patterns
for each V1–V6 output signal.Table V summarizes the registers
available for generating each of the 10 V-pattern groups.The start
polarity (VPOL) determines the starting polarity of the vertical
sequence, and can be programmed high or low for each V1–V6
output.The first, second, and third toggle position (VTOG1,
VTOG2, VTOG3) are the pixel locations within the line where
the pulse transitions. A fourth toggle position (VTOG4) is also
available for V-Pattern Groups 8 and 9. All toggle positions are
12-bit values, allowing their placement anywhere in the hori-
zontal line. A separate register,VPATSTART, specifies the start
position of the V-pattern group within the line (see the Vertical
Sequences section).The VPATLEN register designates the total
length of the V-pattern group, which will determine the number
of pixels between each of the pattern repetitions, when repetitions
are used (see the Vertical Sequences section).
The FREEZE and RESUME registers are used to temporarily
stop the operation of the V1–V6 outputs. At the pixel location
specified in the FREEZE register, the V1–V6 outputs will be
held static at their current dc state, high or low. The V1–V6
outputs are held until the pixel location specified by RESUME
register. Two sets of FREEZE/RESUME registers are pro-
vided, allowing the vertical outputs to be interrupted twice in
the same line. The FREEZE and RESUME positions are pro-
grammed in the V-pattern group registers, but are separately
enabled using the VMASK registers, which are described in the
Vertical Sequence section.
REV. 0
OBSOLETE
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| AD9995KCPZRL | 功能描述:IC CCD SIGNAL PROCESSOR 56-LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件 |
| AD9995KCPZRL7 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9996BBCZ | 制造商:Rochester Electronics LLC 功能描述:14B 40 MSPS AFETG CONVERTER - Bulk |
| AD9996BBCZRL | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD-9FT4-B2 | 制造商:Pan Pacific 功能描述: |
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