參數(shù)資料
型號(hào)： AD9995KCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 14/60頁(yè)
文件大?。?/td> 0K
描述： IC CCD SIGNAL PROCESSOR 56-LFCSP
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： CCD 信號(hào)處理器，12 位
輸入類(lèi)型： 邏輯
輸出類(lèi)型： 邏輯
接口： 3 線串口
電流 - 電源： 30mA
安裝類(lèi)型： 表面貼裝
封裝/外殼： 56-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 56-LFCSP-VQ（8x8）
包裝： 托盤(pán)
AD9995
–21–
Sweep Mode Operation
The AD9995 contains an additional mode of vertical timing
operation called Sweep mode.This mode is used to generate a
large number of repetitive pulses that span multiple HD lines.
One example of where this mode is needed is at the start of the
CCD readout operation. At the end of the image exposure but
before the image is transferred by the sensor gate pulses, the
vertical interline CCD registers should be free of all charge.This
can be accomplished by quickly shifting out any charge using a
long series of pulses from the V1–V6 outputs. Depending on the
vertical resolution of the CCD, up to 2,000 or 3,000 clock cycles
will be needed to shift the charge out of each vertical CCD line.
This operation will span across multiple HD line lengths. Nor-
mally, the AD9995’s vertical timing must be contained within
one HD line length, but when Sweep mode is enabled, the HD
boundaries will be ignored until the region is finished.To enable
Sweep mode within any region, program the appropriate
SWEEP register to high.
Figure 21 shows an example of Sweep mode operation. The
number of vertical pulses needed will depend on the vertical
resolution of the CCD. The V1–V6 output signals are gener-
ated using the V-pattern registers (shown in Table VII). A single
pulse is created using the polarity and toggle position registers.
The number of repetitions is then programmed to match the
number of vertical shifts required by the CCD. Repetitions are
programmed in the V-sequence registers using the VPATREP
registers. This produces a pulse train of the appropriate length.
Normally, the pulse train would be truncated at the end of the
HD line length, but with Sweep mode enabled for this region,
the HD boundaries will be ignored. In Figure 21, the Sweep
region occupies 23 HD lines. After the Sweep mode region is
completed, in the next region, normal sequence operation will
resume. When using Sweep mode, be sure to set the region
boundaries (using the sequence change positions) to the appro-
priate lines to prevent the Sweep operation from overlapping the
next V-sequence.
Multiplier Mode
To generate very wide vertical timing pulses, a vertical region
may be configured into a multiplier region. This mode uses
the V-pattern registers in a slightly different manner. Multiplier
mode can be used to support unusual CCD timing requirements,
such as vertical pulses that are wider than a single HD line length.
The start polarity and toggle positions are still used in the same
manner as the standard VPAT group programming, but the
VPATLEN is used differently. Instead of using the pixel counter
(HD counter) to specify the toggle position locations (VTOG1,
2, 3) of the VPAT group, the VPATLEN is multiplied with the
VTOG position to allow very long pulses to be generated.To cal-
culate the exact toggle position, counted in pixels after the start
position, use the equation
Multiplier ModeTogglePosition VTOG VPATLEN
=
×
Because the VTOG register is multiplied by VPATLEN,
the resolution of the toggle position placement is reduced. If
VPATLEN = 4, the toggle position accuracy is now reduced
to 4-pixel steps instead of single pixel steps. Table VIII sum-
marizes how the VPAT group registers are used in Multiplier
mode operation. In Multiplier mode, the VPATREPO and
VPATREPE registers should always be programmed to the same
value as the highest toggle position.
VD
V1–V6
HD
REGION 1: SWEEP REGION
LINE 0
L
0
LINE 1
REGION 0
REGION 2
LINE 24
LINE 25
LINE 2
SCP 1
SCP 2
Figure 21. Example of Sweep Region for High Speed Vertical Shift
Table VIII. Multiplier Mode Register Parameters
Register
Length
Range
Description
MULTI
1b
High/Low
High enables Multiplier mode.
VPOL
1b
High/Low
Starting Polarity of V1–V6 Signal in Each VPAT Group.
VTOG1
12b
0–4095 Pixel Location
First Toggle Position for V1–V6 Signal in Each VPAT Group.
VTOG2
12b
0–4095 Pixel Location
Second Toggle Position for V1–V6 Signal in Each VPAT Group.
VTOG3
12b
0–4095 Pixel Location
Third Toggle Position for V1–V6 Signal in Each VPAT Group.
VPATLEN
10b
0–1023 Pixels
Used as Multiplier Factor for Toggle Position Counter.
VPATREP
12b
0–4096
VPATREPE/VPATREPO should be set to the same value as TOG2 or 3.
REV. 0
OBSOLETE
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