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參數(shù)資料
| 型號(hào)： | AD9995KCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 47/60頁(yè) |
| 文件大小： | 0K |
| 描述： | IC CCD SIGNAL PROCESSOR 56-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | CCD 信號(hào)處理器，12 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 電流 - 電源： | 30mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 56-LFCSP-VQ（8x8） |
| 包裝： | 托盤 |
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AD9995
–51–
Table XL.V-Sequence 3 (VSEQ3) Register Map
Data Bit Default
Address Content Value
Register Name
Description
98
[1:0]
0
HBLKMASK_3
Masking Polarity during HBLK. H1 [0]. H3 [1].
[2]
0
CLPOBPOL_3
CLPOBPOL
CLPOB Start Polarity
[3]
0
PBLKPOL_3
PBLKPOL
PBLK Start Polarity
[7:4]
0
VPATSEL_3
VPATSEL
Selected V-Pattern Group for V-Sequence 3
[9:8]
0
VMASK_3
VMASK
Enable Masking of V-Outputs (Specified by FREEZE/RESUME Registers)
[11:10]
0
HBLKALT_3
Enable HBLK Alternation
[23:12]
0
UNUSED
Unused
99
[11:0]
0
VPATREPO_3
Number of Selected V-Pattern Group Repetitions for Odd Lines
[23:12]
0
VPATREPE_3
Number of Selected V-Pattern Group Repetitions for Even Lines
9A
[11:0]
0
VPATSTART_3
Start Position in the Line for the Selected V-Pattern Group
[23:12]
0
HDLEN_3
HD Line Length (Number of Pixels) for V-Sequence 3
9B
[11:0]
0
PBLKTOG1_3
PBLK Toggle Position 1 for V-Sequence 3
[23:12]
0
PBLKTOG2_3
PBLK Toggle Position 2 for V-Sequence 3
9C
[11:0]
0
HBLKTOG1_3
HBLK Toggle Position 1 for V-Sequence 3
[23:12]
0
HBLKTOG2_3
HBLK Toggle Position 2 for V-Sequence 3
9D
[11:0]
0
HBLKTOG3_3
HBLK Toggle Position 3 for V-Sequence 3
[23:12]
0
HBLKTOG4_3
HBLK Toggle Position 4 for V-Sequence 3
9E
[11:0]
0
HBLKTOG5_3
HBLK Toggle Position 5 for V-Sequence 3
[23:12]
0
HBLKTOG6_3
HBLK Toggle Position 6 for V-Sequence 3
9F
[11:0]
0
CLPOBTOG1_3
CLPOB Toggle Position 1 for V-Sequence 3
[23:12]
0
CLPOBTOG2_3
CLPOB Toggle Position 2 for V-Sequence 3
Table XLI.V-Sequence 4 (VSEQ4) Register Map
Data Bit Default
Address Content Value
Register Name
Description
A0
[1:0]
0
HBLKMASK_4
Masking Polarity during HBLK. H1 [0]. H3 [1].
[2]
0
CLPOBPOL_4
CLPOBPOL
CLPOB Start Polarity
[3]
0
PBLKPOL_4
PBLKPOL
PBLK Start Polarity
[7:4]
0
VPATSEL_4
VPATSEL
Selected V-Pattern Group for V-Sequence 4
[9:8]
0
VMASK_4
VMASK
Enable Masking of V-Outputs (Specified by FREEZE/RESUME Registers)
[11:10]
0
HBLKALT_4
Enable HBLK Alternation
[23:12]
0
UNUSED
Unused
A1
[11:0]
0
VPATREPO_4
Number of Selected V-Pattern Group Repetitions for Odd Lines
[23:12]
0
VPATREPE_4
Number of Selected V-Pattern Group Repetitions for Even Lines
A2
[11:0]
0
VPATSTART_4
Start Position in the Line for the Selected V-Pattern Group
[23:12]
0
HDLEN_4
HD Line Length (Number of Pixels) for V-Sequence 4
A3
[11:0]
0
PBLKTOG1_4
PBLK Toggle Position 1 for V-Sequence 4
[23:12]
0
PBLKTOG2_4
PBLK Toggle Position 2 for V-Sequence 4
A4
[11:0]
0
HBLKTOG1_4
HBLK Toggle Position 1 for V-Sequence 4
[23:12]
0
HBLKTOG2_4
HBLK Toggle Position 2 for V-Sequence 4
A5
[11:0]
0
HBLKTOG3_4
HBLK Toggle Position 3 for V-Sequence 4
[23:12]
0
HBLKTOG4_4
HBLK Toggle Position 4 for V-Sequence 4
A6
[11:0]
0
HBLKTOG5_4
HBLK Toggle Position 5 for V-Sequence 4
[23:12]
0
HBLKTOG6_4
HBLK Toggle Position 6 for V-Sequence 4
A7
[11:0]
0
CLPOBTOG1_4
CLPOB Toggle Position 1 for V-Sequence 4
[23:12]
0
CLPOBTOG2_4
CLPOB Toggle Position 2 for V-Sequence 4
REV. 0
OBSOLETE
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| AD9995KCPZRL | 功能描述:IC CCD SIGNAL PROCESSOR 56-LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測(cè)器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件 |
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