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參數(shù)資料
| 型號(hào)： | AD9995KCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 45/60頁 |
| 文件大小： | 0K |
| 描述： | IC CCD SIGNAL PROCESSOR 56-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | CCD 信號(hào)處理器，12 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 電流 - 電源： | 30mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 56-LFCSP-VQ（8x8） |
| 包裝： | 托盤 |
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AD9995
–5–
TIMING SPECIFICATIONS (C
L = 20 pF, AVDD = DVDD = DRVDD = 3.0 V, fCLI = 36 MHz, unless otherwise noted.)
Parameter
Symbol
Min
Typ
Max
Unit
MASTER CLOCK, CLI (Figure 4)
CLI Clock Period
tCONV
27.8
ns
CLI High/Low Pulsewidth
11.2
13.9
16.6
ns
Delay from CLI Rising Edge to Internal Pixel Position 0
tCLIDLY
6
ns
AFE CLPOB Pulsewidth1, 2 (Figures 9 and 14)
2
20
Pixels
AFE SAMPLE LOCATION1 (Figure 7)
SHP Sample Edge to SHD Sample Edge
tS1
12.5
13.9
ns
DATA OUTPUTS (Figures 8a and 8b)
Output Delay from DCLK Rising Edge1
tOD
8
ns
Pipeline Delay from SHP/SHD Sampling to DOUT
11
Cycles
SERIAL INTERFACE (Figures 40a and 40b)
Maximum SCK Frequency
fSCLK
ff
10
MHz
SL to SCK Setup Time
tLS
10
ns
SCK to SL Hold Time
tLH
10
ns
SDATA Valid to SCK Rising Edge Setup
tDS
10
ns
SCK Falling Edge to SDATA Valid Hold
tDH
10
ns
SCK Falling Edge to SDATA Valid Read
tDV
10
ns
NOTES
1Parameter is programmable.
2Minimum CLPOB pulsewidth is for functional operation only.Wider typical pulses are recommended to achieve good clamp performance.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
With
Respect
Parameter
To
Min
Max
Unit
AVDD
AVSS
–0.3
+3.9
V
TCVDD
TCVSS
–0.3
+3.9
V
HVDD
HVSS
–0.3
+3.9
V
RGVDD
RGVSS
–0.3
+3.9
V
DVDD
DVSS
–0.3
+3.9
V
DRVDD
DRVSS
–0.3
+3.9
V
RG Output
RGVSS
–0.3
RGVDD+0.3 V
H1–H4 Output
HVSS
–0.3
HVDD + 0.3 V
Digital Outputs
DVSS
–0.3
DVDD + 0.3 V
Digital Inputs
DVSS
–0.3
DVDD + 0.3 V
SCK, SL, SDATA
DVSS
–0.3
DVDD + 0.3 V
REFT, REFB, CCDIN
AVSS
–0.3
AVDD + 0.3 V
Junction Temperature
150
°C
Lead Temperature, 10 sec
350
°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only. Functional operation of the device
at these or any other conditions above those listed in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability. Absolute maximum ratings apply
individually only, not in combination. Unless otherwise specified, all other voltages
are referenced to GND.
PACKAGE THERMAL CHARACTERISTICS
Thermal Resistance
JA = 25°C/W*
*JA is measured using a 4-layer PCB with the exposed paddle soldered to the
board.
ORDERING GUIDE
Temperature
Package
Model
Range
Description
Option
AD9995KCP
–20°C to +85°C
LFCSP
CP-56
AD9995KCPRL
–20°C to +85°C
LFCSP
CP-56
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on
the human body and test equipment and can discharge without detection. Although the AD9995 features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
REV. 0
OBSOLETE
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| AD9995KCPZRL | 功能描述:IC CCD SIGNAL PROCESSOR 56-LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測(cè)器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件 |
| AD9995KCPZRL7 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
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