- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1895 > AD9995KCPZ (Analog Devices Inc)IC CCD SIGNAL PROCESSOR 56-LFCSP PDF資料下載
參數(shù)資料
| 型號： | AD9995KCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/60頁 |
| 文件大小： | 0K |
| 描述： | IC CCD SIGNAL PROCESSOR 56-LFCSP |
| 標(biāo)準包裝： | 1 |
| 類型： | CCD 信號處理器，12 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 電流 - 電源： | 30mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 56-LFCSP-VQ（8x8） |
| 包裝： | 托盤 |
第1頁當(dāng)前第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁
AD9995
–10–
PRECISION TIMING HIGH SPEED TIMING GENERATION
The AD9995 generates high speed timing signals using the
flexible Precision Timing core.This core is the foundation for
generating the timing used for both the CCD and the AFE: the
reset gate RG, horizontal drivers H1–H4, and SHP/SHD sample
clocks. A unique architecture makes it routine for the system
designer to optimize image quality by providing precise control
over the horizontal CCD readout and the AFE correlated double
sampling.
The high speed timing of the AD9995 operates the same in either
Master or Slave mode configuration. For more information on
synchronization and pipeline delays, see the Power-Up and Syn-
chronization section.
Timing Resolution
The Precision Timing core uses a 1 master clock input (CLI)
as a reference.This clock should be the same as the CCD pixel
clock frequency. Figure 4 illustrates how the internal timing core
divides the master clock period into 48 steps or edge positions.
Using a 20 MHz CLI frequency, the edge resolution of the Preci-
sion Timing core is 1 ns. If a 1 system clock is not available, it
is also possible to use a 2 reference clock by programming the
CLIDIVIDE register (Addr. 0x30).The AD9995 will then inter-
nally divide the CLI frequency by 2.
The AD9995 also includes a master clock output, CLO, which is
the inverse of CLI.This output is intended to be used as a crystal
driver. A crystal can be placed between the CLI and CLO pins to
generate the master clock for the AD9995. For more information
on using a crystal, see Figure 39.
High Speed Clock Programmability
Figure 5 shows how the high speed clocks RG, H1–H4, SHP,
and SHD are generated.The RG pulse has programmable rising
and falling edges, and may be inverted using the polarity control.
The horizontal clocks H1 and H3 have programmable rising
and falling edges and polarity control.The H2 and H4 clocks
are always inverses of H1 and H3, respectively. Table I
summarizes the high speed timing registers and their parameters.
Figure 6 shows the typical 2-phase H-clock arrangement in
which H3 and H4 are programmed for the same edge location as
H1 and H2.
The edge location registers are 6 bits wide, but there are only 48
valid edge locations available.Therefore, the register values are
NOTES
PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.
THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (
tCLIDLY = 6ns TYP).
P[0]
P[48] = P[0]
P[12]
P[24]
P[36]
1 PIXEL
PERIOD
CLI
tCLIDLY
POSITION
Figure 4. High Speed Clock Resolution from CLI Master Clock Input
H1
H2
CCD
SIGNAL
RG
PROGRAMMABLE CLOCK POSITIONS:
1. RG RISING EDGE
2. RG FALLING EDGE
3. SHP SAMPLE LOCATION
4. SHD SAMPLE LOCATION
5. H1 RISING EDGE POSITION
7. H3 RISING EDGE POSITION
H3
H4
3
4
1
2
5
6
7
8
6. H1 FALLING EDGE POSITION (H2 IS INVERSE OF H1)
8. H3 FALLING EDGE POSITION (H4 IS INVERSE OF H3)
REV. 0
OBSOLETE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADA4424-6ARUZ | IC FILTR VID6CH SD/ED/HD 38TSSOP |
| ADATE302-02BBCZ | IC DCL ATE 500MHZ DUAL 84CSPBGA |
| ADATE304BBCZ | IC DCL ATE 200MHZ DUAL 84CSPBGA |
| ADATE305BSVZ | IC DCL ATE 250MHZ DUAL 100TQFP |
| ADAU1328BSTZ | IC CODEC 24BIT 2ADC/8DAC 48LQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9995KCPZRL | 功能描述:IC CCD SIGNAL PROCESSOR 56-LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件 |
| AD9995KCPZRL7 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9996BBCZ | 制造商:Rochester Electronics LLC 功能描述:14B 40 MSPS AFETG CONVERTER - Bulk |
| AD9996BBCZRL | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD-9FT4-B2 | 制造商:Pan Pacific 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。