參數(shù)資料
型號： AD9995KCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 31/60頁
文件大?。?/td> 0K
描述： IC CCD SIGNAL PROCESSOR 56-LFCSP
標(biāo)準(zhǔn)包裝： 1
類型： CCD 信號處理器，12 位
輸入類型： 邏輯
輸出類型： 邏輯
接口： 3 線串口
電流 - 電源： 30mA
安裝類型： 表面貼裝
封裝/外殼： 56-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 56-LFCSP-VQ（8x8）
包裝： 托盤
AD9995
–36–
AD9995
–37–
SERIAL INTERFACE TIMING
All of the internal registers of the AD9995 are accessed through
a 3-wire serial interface. Each register consists of an 8-bit address
and a 24-bit data-word. Both the 8-bit address and 24-bit data-
word are written starting with the LSB.To write to each register,
a 32-bit operation is required, as shown in Figure 40a. Although
many registers are fewer than 24 bits wide, all 24 bits must be
written for each register. For example, if the register is only
10 bits wide, the upper 14 bits are don’t cares and may be filled
with 0s during the serial write operation. If fewer than 24 bits are
written, the register will not be updated with new data.
SDATA
A0
A1
A2
A4
A5
A6
A7
D0
D1
D2
D3
D21 D22 D23
SCK
SL
A3
NOTES
1. SDATA BITS ARE LATCHED ON SCK RISING EDGES. SCK MAY IDLE HIGH OR LOW IN BETWEEN WRITE OPERATIONS.
2. ALL 32 BITS MUST BE WRITTEN: 8 BITS FOR ADDRESS AND 24 BITS FOR DATA.
3. IF THE REGISTER LENGTH IS <24 BITS, “DON’T CARE” BITS MUST BE USED TO COMPLETE THE 24-BIT DATA LENGTH.
4. NEW DATA VALUES ARE UPDATED IN THE SPECIFIED REGISTER LOCATION AT DIFFERENT TIMES, DEPENDING ON THE
PARTICULAR REGISTER WRITTEN TO. SEE THE REGISTER UPDATES SECTION FOR MORE INFORMATION.
tDH
tLS
tLH
tDS
...
8-BIT ADDRESS
24-BIT DATA
1
32
2
3
4
5
6
7
8
9
10
11
12
30
31
Figure 40a. Serial Write Operation
SDATA
A0
A1
A2
A4
A5
A6
A7
D0
D1
D22 D23
SCK
SL
A3
NOTES
1. MULTIPLE SEQUENTIAL REGISTERS MAY BE LOADED CONTINUOUSLY.
2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 24-BIT DATA-WORDS.
3. THE ADDRESS WILL AUTOMATICALLY INCREMENT WITH EACH 24-BIT DATA-WORD (ALL 24 BITS MUST BE WRITTEN).
4. SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
D0
D1
D22 D23
D0
...
DATA FOR STARTING
REGISTER ADDRESS
DATA FOR NEXT
REGISTER ADDRESS
D2
D1
...
1
32
2
3
4
5
6
7
8
9
10
31
34
33
56
55
58
57
59
Figure 40b. Continuous Serial Write Operation
Figure 40b shows a more efficient way to write to the registers,
using the AD9995’s address auto-increment capability. Using
this method, the lowest desired address is written first, followed
by multiple 24-bit data-words. Each new 24-bit data-word will
automatically be written to the next highest register address. By
eliminating the need to write each 8-bit address, faster register
loading is achieved. Continuous write operations may be used
starting with any register location, and may be used to write to as
few as two registers, or as many as the entire register space.
REV. 0
OBSOLETE
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