參數(shù)資料
型號(hào)： AD9992BBCZRL
廠商： Analog Devices Inc
文件頁數(shù)： 90/92頁
文件大?。?/td> 0K
描述： IC CCD SGNL PROC 12BIT 105CSPBGA
產(chǎn)品變化通告： AD9992 Discontinuation 22/Feb/2012
標(biāo)準(zhǔn)包裝： 2,000
類型： CCD 信號(hào)處理器，12 位
輸入類型： 邏輯
輸出類型： 邏輯
接口： 3 線串口
電流 - 電源： 27mA
安裝類型： 表面貼裝
封裝/外殼： 105-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 105-CSPBGA（8x8）
包裝： 帶卷 (TR)
AD9992
Rev. C | Page 90 of 92
Address
Data
Bits
Default
Value
Update
Type
Mnemonic
Description
0x1F
[12:0]
X
SCP
HBLKSTARTA
HBLK Repeat Area Start Position A for HBLK Mode 2. Set to 8191 if not used.
[25:13]
X
HBLKSTARTB
HBLK Repeat Area Start Position B for HBLK Mode 2. Set to 8191 if not used.
0x20
[12:0]
X
SCP
HBLKSTARTC
HBLK Repeat Area Start Position C for HBLK Mode 2. Set to 8191 if not used.
[13]
X
VSEQALT_EN
Special V-sequence alternation enable.
[14]
X
VALT_MAP
1: Enables operation of VALTSEL0_EVEN/ODD, VALTSEL1_EVEN/ODD
registers in FREEZE/RESUME registers. Must be enabled if special VALT mode
is used.
[17:15]
X
SPC_PAT_EN
1: Enables use of special vertical pattern insertion into VPATA sequence.
[0]: Use VPATB as the special pattern.
[1]: Use VPATC as the special pattern.
[2]: Use VPATD as the special pattern.
0x21
[2:0]
X
SCP
HBLKALT_PAT1
HBLK Mode 2, Repeat Area 0 pattern for odd lines.
[6:4]
X
HBLKALT_PAT2
HBLK Mode 2, Repeat Area 0 pattern for odd lines.
[10:8]
X
HBLKALT_PAT3
HBLK Mode 2, Repeat Area 0 pattern for odd lines.
[14:12]
X
HBLKALT_PAT4
HBLK Mode 2, Repeat Area 0 pattern for odd lines.
[18:16]
X
HBLKALT_PAT5
HBLK Mode 2, Repeat Area 0 pattern for odd lines.
[22:20]
X
HBLKALT_PAT6
HBLK Mode 2, Repeat Area 0 pattern for odd lines.
0x22
[12:0]
X
SCP
CLPOBTOG1
CLPOB Toggle Position 1.
[25:13]
X
CLPOBTOG2
CLPOB Toggle Position 2.
0x23
[12:0]
X
SCP
PBLKTOG1
PBLK Toggle Position 1.
[25:13]
X
PBLKTOG2
PBLK Toggle Position 2.
0x24
[12:0]
X
SCP
LASTREPLEN_A
Last repetition length for Group A. Set equal to VLENA.
[25:13]
X
LASTREPLEN_B
Last repetition length for Group B. Set equal to VLENB.
0x25
[12:0]
X
SCP
LASTREPLEN_C
Last repetition length for Group C. Set equal to VLENC.
[25:13]
X
LASTREPLEN_D
Last repetition length for Group D. Set equal to VLEND.
0x26
[12:0]
X
SCP
LASTTOG_A
Optional fifth toggle position for Group A.
[25:13]
X
LASTTOG_B
Optional fifth toggle position for Group B.
0x27
[12:0]
X
SCP
LASTTOG_C
Optional fifth toggle position for Group C.
[25:13]
X
LASTTOG_D
Optional fifth toggle position for Group D.
Table 42. Field Registers
Address
Data
Bits
Default
Value
Update
Type
Mnemonic
Description
0x00
[4:0]
X
VD
SEQ0
Selected V-sequence for first region in the field.
[9:5]
X
SEQ1
Selected V-sequence for second region in the field.
[14:10]
X
SEQ2
Selected V-sequence for third region in the field.
[19:15]
X
SEQ3
Selected V-sequence for fourth region in the field.
[24:20]
X
SEQ4
Selected V-sequence for fifth region in the field.
0x01
[4:0]
X
VD
SEQ5
Selected V-sequence for sixth region in the field.
[9:5]
X
SEQ6
Selected V-sequence for seventh region in the field.
[14:10]
X
SEQ7
Selected V-sequence for eighth region in the field.
[19:15]
X
SEQ8
Selected V-sequence for ninth region in the field.
[21:20]
MULT_SWEEP0
Enables multiplier mode and/or sweep mode for Region 0:
0: Multiplier off/sweep off.
1: Multiplier off/sweep on.
2: Multiplier on/sweep off.
3: Multiplier on/sweep on.
[23:22]
MULT_SWEEP1
Enables multiplier mode and/or sweep mode for Region 2.
[25:24]
MULT_SWEEP2
Enables multiplier mode and/or sweep mode for Region 1.
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