- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗1895 > AD9992BBCZRL (Analog Devices Inc)IC CCD SGNL PROC 12BIT 105CSPBGA PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | AD9992BBCZRL |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 10/92闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC CCD SGNL PROC 12BIT 105CSPBGA |
| 鐢�(ch菐n)鍝佽畩鍖栭€氬憡锛� | AD9992 Discontinuation 22/Feb/2012 |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 2,000 |
| 椤炲瀷锛� | CCD 淇¤櫉铏曠悊鍣紝12 浣� |
| 杓稿叆椤炲瀷锛� | 閭忚集 |
| 杓稿嚭椤炲瀷锛� | 閭忚集 |
| 鎺ュ彛锛� | 3 绶氫覆鍙� |
| 闆绘祦 - 闆绘簮锛� | 27mA |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 105-LFBGA锛孋SPBGA |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 105-CSPBGA锛�8x8锛� |
| 鍖呰锛� | 甯跺嵎 (TR) |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�鐣�(d膩ng)鍓嶇10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�绗�91闋�绗�92闋�
AD9992
Rev. C | Page 18 of 92
P[0]
P[64] = P[0]
PIXEL
PERIOD
P[16]
P[32]
P[48]
DOUT
DCLK
tOD
NOTES
1. DATA OUTPUT (DOUT) AND DCLK PHASE ARE ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD.
2. WITHIN ONE CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO 64 DIFFERENT LOCATIONS.
3. DCLK CAN BE INVERTED WITH RESPECT TO DOUT BY USING THE DCLKINV REGISTER.
05
89
1-
02
0
Figure 20. Digital Output Phase Adjustment Using DOUTPHASEP Register
NOTES
1. TIMING VALUES SHOWN ARE SHDLOC = 0, WITH DCLKMODE = 0.
2. HIGHER VALUES OF SHD AND/OR DOUT PHASE SHIFTS DOUT TRANSITION TO THE RIGHT, WITH RESPECT TO CLI LOCATION.
3. RECOMMENDED VALUE FOR DOUT PHASE IS TO USE SHPLOC OR UP TO 15 EDGES FOLLOWING SHPLOC.
DCLK
DOUT
CCDIN
CLI
SHD
(INTERNAL)
ADC DOUT
(INTERNAL)
NN + 2
N + 1
N + 3
N + 13
N + 12
N + 11
N + 10
N + 9
N + 8
N + 7
N + 6
N + 5
N + 4
N + 14
SAMPLE PIXEL N
N + 16
N + 17
N + 15
N 鈥� 14
N 鈥� 4
N 鈥� 5
N 鈥� 6
N 鈥� 7
N 鈥� 8
N 鈥� 9
N 鈥� 10
N 鈥� 11
N 鈥� 12
N 鈥� 13
N 鈥� 3
N 鈥� 2
N 鈥� 1
N
N + 1
N 鈥� 15
N 鈥� 16
N 鈥� 17
tCLIDLY
PIPELINE LATENCY = 16 CYCLES
N 鈥� 14
N 鈥� 4
N 鈥� 5
N 鈥� 6
N 鈥� 7
N 鈥� 8
N 鈥� 9
N 鈥� 10
N 鈥� 11
N 鈥� 12
N 鈥� 13
N 鈥� 3
N 鈥� 2
N 鈥� 1
N
N + 1
N 鈥� 15
N 鈥� 16
N 鈥� 17
tDOUTINH
05891-
021
Figure 21. Digital Data Output Pipeline Delay
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| AD9995KCPZ | IC CCD SIGNAL PROCESSOR 56-LFCSP |
| ADA4424-6ARUZ | IC FILTR VID6CH SD/ED/HD 38TSSOP |
| ADATE302-02BBCZ | IC DCL ATE 500MHZ DUAL 84CSPBGA |
| ADATE304BBCZ | IC DCL ATE 200MHZ DUAL 84CSPBGA |
| ADATE305BSVZ | IC DCL ATE 250MHZ DUAL 100TQFP |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| AD9993BBCZ | 鍔熻兘鎻忚堪:IC MIXED-SIGNAL FRONT END 196BGA 鍒堕€犲晢:analog devices inc. 绯诲垪:- 鍖呰:鎵樼洡 闆朵欢鐙€鎱�(t脿i):鍦ㄥ敭 椤炲瀷:ADC锛孌AC 杓稿叆椤炲瀷:LVDS 杓稿嚭椤炲瀷:LVDS 鎺ュ彛:SPI 闆绘祦 - 闆绘簮:- 宸ヤ綔婧害:- 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:196-LFBGA锛孋SPBGA 渚涙噳(y墨ng)鍟嗗櫒浠跺皝瑁�:196-CSPBGA锛�12x12锛� 妯�(bi膩o)婧�(zh菙n)鍖呰:1 |
| AD9993BBCZRL | 鍔熻兘鎻忚堪:IC MIXED-SIGNAL FRONT END 196BGA 鍒堕€犲晢:analog devices inc. 绯诲垪:- 鍖呰:甯跺嵎锛圱R锛� 闆朵欢鐙€鎱�(t脿i):鍦ㄥ敭 椤炲瀷:ADC锛孌AC 杓稿叆椤炲瀷:LVDS 杓稿嚭椤炲瀷:LVDS 鎺ュ彛:SPI 闆绘祦 - 闆绘簮:- 宸ヤ綔婧害:- 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:196-LFBGA锛孋SPBGA 渚涙噳(y墨ng)鍟嗗櫒浠跺皝瑁�:196-CSPBGA锛�12x12锛� 妯�(bi膩o)婧�(zh菙n)鍖呰:1,500 |
| AD9993-EBZ | 鍔熻兘鎻忚堪:EVAL BOARD MXFE AD9993 鍒堕€犲晢:analog devices inc. 绯诲垪:* 闆朵欢鐙€鎱�(t脿i):鍦ㄥ敭 妯�(bi膩o)婧�(zh菙n)鍖呰:1 |
| AD9994 | 鍒堕€犲晢:AD 鍒堕€犲晢鍏ㄧū:Analog Devices 鍔熻兘鎻忚堪:12-Bit CCD Signal Processor with Precision Timing Generator |
| AD9994BCP | 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:AFE GEN PURPOSE 12-BIT 64LFCSP - Bulk |
鐧�(f膩)甯冪穵鎬ラ噰璩�锛�3鍒嗛悩宸﹀彸鎮ㄥ皣寰楀埌鍥炲京(f霉)銆�
