參數(shù)資料
型號(hào)： AD9992BBCZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 7/92頁(yè)
文件大?。?/td> 0K
描述： IC CCD SGNL PROC 12BIT 105CSPBGA
產(chǎn)品變化通告： AD9992 Discontinuation 22/Feb/2012
標(biāo)準(zhǔn)包裝： 2,000
類型： CCD 信號(hào)處理器，12 位
輸入類型： 邏輯
輸出類型： 邏輯
接口： 3 線串口
電流 - 電源： 27mA
安裝類型： 表面貼裝
封裝/外殼： 105-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 105-CSPBGA（8x8）
包裝： 帶卷 (TR)
AD9992
Rev. C | Page 15 of 92
HIGH SPEED PRECISION TIMING CORE
The AD9992 generates high speed timing signals using the flexible
Precision Timing core. This core is the foundation for generating
timing used for both the CCD and the AFE; it includes the reset
gate RG, horizontal drivers H1 to H8, HL, and SHP/SHD sample
clocks. A unique architecture makes it routine for the system
designer to optimize image quality by providing precise control
over the horizontal CCD readout and the AFE correlated
double sampling.
The high speed timing of the AD9992 operates the same way in
either master or slave mode configuration. For more informa-
tion on synchronization and pipeline delays, see the Power-Up
Timing Resolution
The Precision Timing core uses a 1× master clock input (CLI) as
a reference. This clock should be the same as the CCD pixel
clock frequency. Figure 15 illustrates how the internal timing
core divides the master clock period into 64 steps or edge
positions. Using a 40 MHz CLI frequency, the edge resolution of
the Precision Timing core is approximately 0.4 ns. If a 1× system
clock is not available, it is possible to use a 2× reference clock by
programming the CLIDIVIDE register (AFE Register
Address 0x0D). The AD9992 then internally divides the CLI
frequency by 2.
The AD9992 includes a master clock output (CLO) which
is the inverse of CLI. This output should be used as a crystal
driver. A crystal can be placed between the CLI and CLO pins
to generate the master clock for the AD9992.
High Speed Clock Programmability
Figure 16 shows when the high speed clocks RG, H1 to H8,
SHP, and SHD are generated. The RG pulse has programmable
rising and falling edges and can be inverted using the polarity
control. Horizontal Clock H1 has programmable rising and
falling edges and polarity control. In HCLK Mode 1, H3, H5,
and H7 are equal to H1. H2, H4, H6, and H8 are always inverses
of H1.
The edge location registers are each six bits wide, allowing
selection of all 64 edge locations. Figure 19 shows the default
timing locations for all high speed clock signals.
P[0]
P[64] = P[0]
P[16]
P[32]
P[48]
ONE PIXEL
PERIOD
CLI
tCLIDLY
POSITION
NOTES
1. THE PIXEL CLOCK PERIOD IS DIVIDED INTO 64 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.
2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITION (tCLIDLY).
05
89
1-
0
15
Figure 15. High Speed Clock Resolution from CLI, Master Clock Input
HL
CCD
SIGNAL
RG
PROGRAMMABLE CLOCK POSITIONS:
1SHP SAMPLE LOCATION.
2SHD SAMPLE LOCATION.
3RG RISING EDGE.
4RG FALLING EDGE.
5H1 RISING EDGE.
6H1 FALLING EDGE.
7HL RISING EDGE.
8HL FALLING EDGE.
1
2
34
78
H2, H4, H6, H8
H1, H3, H5, H7
56
0
58
91
-01
6
Figure 16. High Speed Clock Programmable Locations (HCLKMODE = 001)
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