- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1895 > AD9992BBCZRL (Analog Devices Inc)IC CCD SGNL PROC 12BIT 105CSPBGA PDF資料下載
參數(shù)資料
| 型號： | AD9992BBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 72/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD SGNL PROC 12BIT 105CSPBGA |
| 產(chǎn)品變化通告： | AD9992 Discontinuation 22/Feb/2012 |
| 標準包裝： | 2,000 |
| 類型： | CCD 信號處理器，12 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 電流 - 電源： | 27mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 105-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 105-CSPBGA（8x8） |
| 包裝： | 帶卷 (TR) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁當前第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁
AD9992
Rev. C | Page 74 of 92
UPDATING NEW REGISTER VALUES
The AD9992 internal registers are updated at different times,
depending on the particular register. Table 28 summarizes the four
register update types: SCK, VD, SG-Line, and SCP. Tables in the
Complete Register Listing section also contain an Update Type
column that identifies when each register is updated.
SCK Updated—As soon as the 28th data bit (D27) is clocked
in, some registers are immediately updated. These registers
are used for functions that do not require gating with the next
VD boundary, such as power-up and reset functions.
VD Updated—More registers are updated at the next VD
falling edge. By updating these values at the next VD edge,
the current field is not corrupted and the new register
values are applied to the next field. The VD update can be
further delayed past the VD falling edge by using the
UPDATE register (Address 0x17). This delays the VD-
updated register updates to any HD line in the field. Note
that the field registers are not affected by the UPDATE
register.
SG-Line Updated—A few of the shutter registers are updated
at the HD falling edge at the start of the SG active line.
These registers control the SUBCK signal so that the SUBCK
output is not updated until the SG line occurs.
SCP Updated—At the next SCP where they are used,
the V-pattern group and V-sequence registers are updated.
For example, in Figure 87 this field has selected Region 1 to
use VSEQ3 for the vertical outputs. This means that a write
to any of the VSEQ3 registers, or any of the V-pattern
group registers, which are referenced by VSEQ3, updates at
SCP1. If multiple writes are made to the same register, the last
one done before SCP1 is the one that is updated. Likewise,
register writes to any VSEQ5 registers are updated at SCP2;
register writes to any VSEQ8 registers are updated at SCP3.
Caution
It is recommended that the registers in the configurable address
area not be written within 36 pixels of any HD falling edge
where a sequence change position (SCP) occurs. See Figure 78
and Figure 79 for examples of what this inhibit area looks like in
master and slave modes. This restriction applies to the V-pattern,
V-sequence, and field registers. As shown in Figure 87, writing
to these registers before the VD falling edge typically avoids
loading these registers during SCP locations.
Table 28. Register Update Locations
Update Type
Description
SCK
When the 28th data bit (D27) is clocked in, the register is immediately updated.
VD
Register is updated at the VD falling edge. VD-updated registers can be delayed further by using the UPDATE register at
Address 0x17. FIELD registers are not affected by the UPDATE register.
SG-Line
Register is updated at the HD falling edge at the start of the SG-active line.
SCP
Register is updated at the next SCP when the register is used.
VD
REGION 0
HD
SCP1
SCP2
SCP3
REGION 1
REGION 2
REGION 3
VSG
SGLINE
SCP0
SERIAL
WRITE
SCK
UPDATED
SCP0
VD
UPDATED
SG
UPDATED
SCP
UPDATED
XV1 TO XV24
USE VSEQ2
USE VSEQ3
USE VSEQ5
USE VSEQ8
05
89
1-
0
82
Figure 87. Register Update Locations (See Table 28 for Definitions)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9995KCPZ | IC CCD SIGNAL PROCESSOR 56-LFCSP |
| ADA4424-6ARUZ | IC FILTR VID6CH SD/ED/HD 38TSSOP |
| ADATE302-02BBCZ | IC DCL ATE 500MHZ DUAL 84CSPBGA |
| ADATE304BBCZ | IC DCL ATE 200MHZ DUAL 84CSPBGA |
| ADATE305BSVZ | IC DCL ATE 250MHZ DUAL 100TQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9993BBCZ | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應(yīng)商器件封裝:196-CSPBGA（12x12） 標準包裝:1 |
| AD9993BBCZRL | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應(yīng)商器件封裝:196-CSPBGA（12x12） 標準包裝:1,500 |
| AD9993-EBZ | 功能描述:EVAL BOARD MXFE AD9993 制造商:analog devices inc. 系列:* 零件狀態(tài):在售 標準包裝:1 |
| AD9994 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit CCD Signal Processor with Precision Timing Generator |
| AD9994BCP | 制造商:Analog Devices 功能描述:AFE GEN PURPOSE 12-BIT 64LFCSP - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。