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| 型號(hào)： | AD9992BBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 46/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD SGNL PROC 12BIT 105CSPBGA |
| 產(chǎn)品變化通告： | AD9992 Discontinuation 22/Feb/2012 |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | CCD 信號(hào)處理器，12 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 電流 - 電源： | 27mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 105-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 105-CSPBGA（8x8） |
| 包裝： | 帶卷 (TR) |
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AD9992
Rev. C | Page 50 of 92
FIELD COUNTERS
The AD9992 contains three field counters (primary, secondary,
and mode). When these counters are active, they increment
with each VD cycle. The mode counter is the field counter used
with the mode register to control the vertical timing signals (see
the MODE Registers section. The primary and secondary
counters are more flexible and are generally used for shuttering
signal applications. Both the primary and secondary counters
have several modes of operation that are dictated by Address
0x70, including
Normal (single count)
RapidShot (repeating count)
ShotDelay (delayed count)
ShotDelay with RapidShot
Manual exposure
Manual readout
Force to idle
The primary counter regulates the expose and read actions by
regulating the SUBCK and VSG signals. If the RapidShot
feature is used with the primary counter, the SUBCK and VSG
masking automatically repeats as necessary for multiple expose/
read cycles. The secondary counter has no effect on the SUBCK
or VSG signal. Both counters can be used to regulate the general-
purpose signals described in the General-Purpose Outputs
(GPOs) section.
Table 22. Primary/Secondary Field Counter Registers (Address 0x70, Address 0x71, and Address 0x72)
Register
Length
Description
PRIMARY_ACTION
3b
0: Idle, no counter action. GPO signals can still be controlled using polarity or GP_PROTOCOL = 1.
SECOND_ACTION
3b
1: Activate counter. Single cycle of counter from 1 to counter maximum value, and then returns to idle state.
2: RapidShot. After reaching maximum counter value, counter wraps and repeats until reset.
3: ShotTimer. Active single cycle of counter after added delay of N fields (use the corresponding DELAY
register).
4: ShotTimer with RapidShot. Same as 2, with added delay of N fields between each repetition.
5: Manual exposure. Primary counter stays in exposure until manual readout or reset to idle.
This mode keeps the SUBCK and VSG pulses masked indefinitely.
6: Manual readout. Primary counter switches to readout (VSG pulses becomes active).
7: Force to idle.
PRIMARY_MAX
13b
Primary counter maximum value.
SECOND_MAX
12b
Secondary counter maximum value.
VDHD_MASK
3b
Mask VD/HD during counter operation.
PRIMARY_DELAY
13b
ShotTimer. Number of fields to delay before the next primary count (exposure) starts. If using ShotTimer
with RapidShot, delay value is used between each repeat.
PRIMARY_SKIP
1b
When using ShotTimer with RapidShot, use primary delay value only before first count (exposure).
SECOND_DELAY
13b
ShotTimer. Number of fields to delay before the next secondary count starts. If using ShotTimer with
RapidShot, delay value is used between each repeat.
SECOND_SKIP
1b
When using ShotTimer with RapidShot, use secondary delay value only before first count.
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| AD9993BBCZ | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應(yīng)商器件封裝:196-CSPBGA（12x12） 標(biāo)準(zhǔn)包裝:1 |
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